308 lines
8.1 KiB
C
308 lines
8.1 KiB
C
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/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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#ifdef CONFIG_PHY_VENDOR_USB
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#include <asm/arch-gk7202v300/platform.h>
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#include <dm.h>
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#include "../../usb/host/xhci.h"
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#include "phy-usb.h"
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/* offset 0x140 */
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#define USB2_CTRL 0x140
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#define USB2_CRG_DEFAULT_VAL 0x3b2f
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#define USB2_UTMI_CKEN (0x1 << 12)
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#define USB2_PHY_APB_CKEN (0x1 << 11)
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#define USB2_REF_CKEN (0x1 << 9)
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#define USB2_BUS_CKEN (0x1 << 8)
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#define USB2_PHY_PLL_CKEN (0x1 << 4)
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#define USB2_PHY_XTAL_CKEN (0x1 << 2)
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#define USB2_FREECLK_CKSEL (0x1 << 13)
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#define USB2_PHY_APB_RST (0x1 << 10)
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#define USB2_VCC_SRST_REQ (0x1 << 3)
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#define USB2_PHY_REQ (0x1 << 0)
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#define USB2_PHY_PORT_TREQ (0x1 << 1)
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#define GTXTHRCFG 0xc108
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#define GRXTHRCFG 0xc10c
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#define REG_GCTL 0xc110
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#define REG_GUSB3PIPECTL0 0xc2c0
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#define PCS_SSP_SOFT_RESET (0x1 << 31)
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#define PORT_CAP_DIR (0x3 << 12)
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#define PORT_SET_HOST (0x1 << 12)
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#define PORT_DISABLE_SUSPEND (0x1 << 17)
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#define USB2_G_TXTHRCFG 0x23100000
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#define USB2_G_RXTHRCFG 0x23100000
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/* PHY base register */
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#define USB2_PHY_BASE_REG 0x100D0000
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#define RG_PLL_EN_MASK 0x0003
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#define RG_PLL_EN_VAL 0x0003
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#define PHY_PLL_OFFSET 0x0014
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#define USB_VBUS_IO_CONFIG_REG 0x100c007C
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#define USB_VBUS_IO_CONFIG_VAL 0x0531
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#define USB_PWREN_CONFIG_REG 0x100c0080
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#define USB_PWREN_CONFIG_VAL 0x1
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/* PHY eye config */
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#define PHY_ANA_CFG_0_OFFSET 0x00
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#define PHY_PRE_DRIVE_MASK (0xf << 24)
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#define PHY_PRE_DRIVE_VAL (0x4 << 24)
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#define PHY_HSTX_DE_MASK (0xf << 8)
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#define PHY_HSTX_DE_VAL (0xc << 8)
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#define PHY_HSTX_DEEN_BIT (0x1 << 5)
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#define PHY_ANA_CFG_2_OFFSET 0x08
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#define PHY_TX_TEST_BIT (0x1 << 20)
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#define PHY_HALF_DEEM_BIT (0x1 << 21)
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#define PHY_DISCONNECT_REFERENCE_MASK (0x7 << 16)
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#define PHY_DISCONNECT_REFERENCE_VAL (0x2 << 16)
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#define PHY_ANA_CFG_4_OFFSET 0x10
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#define PHY_TX_REFERENCE_MASK (0x7 << 4)
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#define PHY_TX_REFERENCE_VAL (0x5 << 4)
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#define PHY_SQUELCH_REFERENCE_MASK (0x7 << 0)
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#define PHY_SQUELCH_REFERENCE_VAL (0x5 << 0)
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/* PHY trim config */
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#define USB_TRIM_BASE_REG 0x12028004
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#define USB_TRIM_VAL_MASK 0x001F
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#define USB_TRIM_VAL_MIN 0x0009
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#define USB_TRIM_VAL_MAX 0x001D
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#define USB2_TRIM_OFFSET 0x0008
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#define USB2_TRIM_MASK 0x1f00
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#define usb2_trim_val(a) (((a) << 8) & USB2_TRIM_MASK)
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#define USB2_TRIM_DEFAULT_VAL 0x000F
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static uintptr_t xhci_base = 0;
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int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
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{
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if ((hccr == NULL) || (hcor == NULL))
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return -EINVAL;
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xhci_base = USB3_CTRL_REG_BASE;
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*hccr = (struct xhci_hccr *)(xhci_base);
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*hcor = (struct xhci_hcor *)((uintptr_t) *hccr +
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HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
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return 0;
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}
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void usb2_eye_config(void)
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{
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unsigned int reg;
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/* HSTX pre-drive strength */
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reg = readl(USB2_PHY_BASE_REG + PHY_ANA_CFG_0_OFFSET);
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reg &= ~PHY_PRE_DRIVE_MASK;
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reg |= PHY_PRE_DRIVE_VAL;
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writel(reg, USB2_PHY_BASE_REG + PHY_ANA_CFG_0_OFFSET);
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/* HSTX de-emphasis strength */
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reg = readl(USB2_PHY_BASE_REG + PHY_ANA_CFG_0_OFFSET);
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reg &= ~PHY_HSTX_DE_MASK;
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reg |= PHY_HSTX_DE_VAL;
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writel(reg, USB2_PHY_BASE_REG + PHY_ANA_CFG_0_OFFSET);
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/* HSTX de-emphasis enable */
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reg = readl(USB2_PHY_BASE_REG + PHY_ANA_CFG_0_OFFSET);
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reg |= PHY_HSTX_DEEN_BIT;
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writel(reg, USB2_PHY_BASE_REG + PHY_ANA_CFG_0_OFFSET);
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/* TX test bit */
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reg = readl(USB2_PHY_BASE_REG + PHY_ANA_CFG_2_OFFSET);
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reg |= PHY_TX_TEST_BIT;
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writel(reg, USB2_PHY_BASE_REG + PHY_ANA_CFG_2_OFFSET);
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/* TX half de-emphasis bit */
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reg = readl(USB2_PHY_BASE_REG + PHY_ANA_CFG_2_OFFSET);
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reg |= PHY_HALF_DEEM_BIT;
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writel(reg, USB2_PHY_BASE_REG + PHY_ANA_CFG_2_OFFSET);
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/* Disconnect reference voltage sel */
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reg = readl(USB2_PHY_BASE_REG + PHY_ANA_CFG_2_OFFSET);
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reg &= ~PHY_DISCONNECT_REFERENCE_MASK;
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reg |= PHY_DISCONNECT_REFERENCE_VAL;
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writel(reg, USB2_PHY_BASE_REG + PHY_ANA_CFG_2_OFFSET);
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/* TX reference voltage sel */
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reg = readl(USB2_PHY_BASE_REG + PHY_ANA_CFG_4_OFFSET);
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reg &= ~PHY_TX_REFERENCE_MASK;
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reg |= PHY_TX_REFERENCE_VAL;
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writel(reg, USB2_PHY_BASE_REG + PHY_ANA_CFG_4_OFFSET);
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/* Squlech reference voltage sel */
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reg = readl(USB2_PHY_BASE_REG + PHY_ANA_CFG_4_OFFSET);
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reg &= ~PHY_SQUELCH_REFERENCE_MASK;
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reg |= PHY_SQUELCH_REFERENCE_VAL;
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writel(reg, USB2_PHY_BASE_REG + PHY_ANA_CFG_4_OFFSET);
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}
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void usb2_trim_config(void)
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{
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unsigned int ret;
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unsigned int reg;
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unsigned int trim_val;
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ret = readl(USB_TRIM_BASE_REG);
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trim_val = (ret & USB_TRIM_VAL_MASK); /* get usb trim value */
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reg = readl(USB2_PHY_BASE_REG + USB2_TRIM_OFFSET);
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reg &= ~USB2_TRIM_MASK;
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if ((trim_val >= USB_TRIM_VAL_MIN) && (trim_val <= USB_TRIM_VAL_MAX))
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reg |= usb2_trim_val(trim_val);
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else
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reg |= usb2_trim_val(USB2_TRIM_DEFAULT_VAL);
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writel(reg, USB2_PHY_BASE_REG + USB2_TRIM_OFFSET);
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}
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void phy_usb_init_crg_clk(int index)
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{
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unsigned int reg;
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/* set usb2 CRG default val */
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reg = USB2_CRG_DEFAULT_VAL;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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udelay(U_LEVEL6);
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/* open UTMI clk */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg |= USB2_UTMI_CKEN;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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/* open phy apb clk */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg |= USB2_PHY_APB_CKEN;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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/* open ctrl ref clk */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg |= USB2_REF_CKEN;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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/* open bus clk */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg |= USB2_BUS_CKEN;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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/* open phy pll clk */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg |= USB2_PHY_PLL_CKEN;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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/* open phy xtal clk */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg |= USB2_PHY_XTAL_CKEN;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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/* freeclk_cksel_free */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg |= USB2_FREECLK_CKSEL;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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udelay(U_LEVEL5);
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}
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void phy_usb_init(int index)
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{
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unsigned int reg;
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/* VBUS config */
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reg = USB_VBUS_IO_CONFIG_VAL;
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writel(reg, USB_VBUS_IO_CONFIG_REG);
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reg = USB_PWREN_CONFIG_VAL;
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writel(reg, USB_PWREN_CONFIG_REG);
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/* init crg and clk */
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phy_usb_init_crg_clk(index);
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/* release phy apb */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg &= ~USB2_PHY_APB_RST;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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udelay(U_LEVEL5);
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/* por noreset */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg &= ~USB2_PHY_REQ;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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reg = readl(USB2_PHY_BASE_REG + PHY_PLL_OFFSET);
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reg &= ~RG_PLL_EN_MASK;
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reg |= RG_PLL_EN_VAL;
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writel(reg, USB2_PHY_BASE_REG + PHY_PLL_OFFSET);
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udelay(U_LEVEL10);
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/* cancel TPOR */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg &= ~USB2_PHY_PORT_TREQ;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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udelay(U_LEVEL6);
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/* vcc reset */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg &= ~USB2_VCC_SRST_REQ;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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/* USB2 Controller configs */
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reg = readl(USB3_CTRL_REG_BASE + REG_GUSB3PIPECTL0);
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reg |= PCS_SSP_SOFT_RESET;
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writel(reg, USB3_CTRL_REG_BASE + REG_GUSB3PIPECTL0);
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udelay(U_LEVEL2);
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reg = readl(USB3_CTRL_REG_BASE + REG_GCTL);
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reg &= ~PORT_CAP_DIR;
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reg |= PORT_SET_HOST; /* [13:12] 01: Host; 10: Device; 11: OTG */
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writel(reg, USB3_CTRL_REG_BASE + REG_GCTL);
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udelay(U_LEVEL2);
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reg = readl(USB3_CTRL_REG_BASE + REG_GUSB3PIPECTL0);
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reg &= ~PCS_SSP_SOFT_RESET;
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reg &= ~PORT_DISABLE_SUSPEND; /* disable suspend */
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writel(reg, USB3_CTRL_REG_BASE + REG_GUSB3PIPECTL0);
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udelay(U_LEVEL2);
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writel(USB2_G_TXTHRCFG, USB3_CTRL_REG_BASE + GTXTHRCFG);
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writel(USB2_G_RXTHRCFG, USB3_CTRL_REG_BASE + GRXTHRCFG);
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udelay(U_LEVEL2);
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/* USB2 eye config */
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usb2_eye_config();
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/* USB2 trim config */
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usb2_trim_config();
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}
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EXPORT_SYMBOL(phy_usb_init);
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void xhci_hcd_stop(int index)
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{
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unsigned int reg;
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/* por noreset */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg |= USB2_PHY_REQ;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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udelay(U_LEVEL10);
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/* cancel TPOR */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg |= USB2_PHY_PORT_TREQ;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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udelay(U_LEVEL6);
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/* vcc reset */
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reg = readl(CRG_REG_BASE + USB2_CTRL);
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reg |= USB2_VCC_SRST_REQ;
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writel(reg, CRG_REG_BASE + USB2_CTRL);
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}
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EXPORT_SYMBOL(xhci_hcd_stop);
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#endif
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