491 lines
12 KiB
C
491 lines
12 KiB
C
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/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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#include <stdarg.h>
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#include <command.h>
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#include "ddr_interface.h"
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#include "ddr_training_impl.h"
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/* ddr training cmd result */
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struct ddr_training_result_st ddrt_result_sram;
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static unsigned int ddr_training_addr_start;
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static unsigned int ddr_training_addr_end;
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static int ddr_print_level = DDR_LOG_ERROR;
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#ifdef DDR_TRAINING_LOG_CONFIG
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/* Log ddr training info. */
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void ddr_training_log(const char *func, int level, const char *fmt, ...)
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{
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va_list args;
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if (ddr_print_level > level)
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return;
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DDR_PUTC('[');
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switch (level) {
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case DDR_LOG_INFO:
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DDR_PUTS("INFO");
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break;
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case DDR_LOG_DEBUG:
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DDR_PUTS("DEBUG");
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break;
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case DDR_LOG_WARNING:
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DDR_PUTS("WARNING");
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break;
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case DDR_LOG_ERROR:
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DDR_PUTS("ERROR");
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break;
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case DDR_LOG_FATAL:
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DDR_PUTS("FATAL");
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break;
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default:
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break;
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}
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DDR_PUTC(']');
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DDR_PUTC('[');
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DDR_PUTS(func);
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DDR_PUTC(']');
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va_start(args, fmt);
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while (*fmt != '\0') {
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if (*fmt != '%') {
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DDR_PUTC(*fmt);
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} else {
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fmt++;
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switch (*fmt) {
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case 'x':
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case 'X':
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DDR_PUTS("0x");
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DDR_PUT_HEX(va_arg(args, int));
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break;
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default:
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DDR_PUTC('%');
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DDR_PUTC(*fmt);
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break;
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} /* switch */
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}
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fmt++;
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} /* while */
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va_end(args);
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DDR_PUTS("\r\n");
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}
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/* Nothing to do in DDR command when defined DDR_TRAINING_LOG_CONFIG. */
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void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq)
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{
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return;
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}
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#else
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/* Display DDR training error. */
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void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq)
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{
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switch (mask) {
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case DDR_ERR_WL:
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DDR_PUTS("WL");
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break;
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case DDR_ERR_HW_GATING:
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DDR_PUTS("HW Gate");
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break;
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case DDR_ERR_GATING:
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DDR_PUTS("Gate");
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break;
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case DDR_ERR_DDRT_TIME_OUT:
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DDR_PUTS("DDRT");
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break;
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case DDR_ERR_HW_RD_DATAEYE:
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DDR_PUTS("HW Dataeye");
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break;
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case DDR_ERR_MPR:
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DDR_PUTS("MPR");
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break;
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case DDR_ERR_DATAEYE:
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DDR_PUTS("Dataeye");
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break;
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case DDR_ERR_LPCA:
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DDR_PUTS("LPCA");
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break;
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default:
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break;
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}
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DDR_PUTS(" Err:");
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if (phy != 0) {
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DDR_PUTS(" Phy:");
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DDR_PUT_HEX(phy);
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}
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if (byte != -1) {
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DDR_PUTS(" Byte:");
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DDR_PUT_HEX(byte);
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}
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if (dq != -1) {
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DDR_PUTS(" DQ:");
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DDR_PUT_HEX(dq);
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}
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DDR_PUTS("\r\n");
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}
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#endif
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/* Inint ddr training cmd result */
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static void ddr_training_result_init(struct ddr_cfg_st *cfg, struct ddr_training_result_st *ddrtr_res)
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{
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int i, j;
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ddrtr_memset(ddrtr_res, 0, sizeof(struct ddr_training_result_st));
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ddrtr_res->phy_num = cfg->phy_num;
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for (i = 0; i < cfg->phy_num; i++) {
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ddrtr_res->phy_st[i].rank_num = cfg->phy[i].rank_num;
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for (j = 0; j < cfg->phy[i].rank_num; j++) {
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ddrtr_res->phy_st[i].rank_st[j].item = cfg->phy[i].rank[j].item;
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ddrtr_res->phy_st[i].rank_st[j].ddrtr_data.base_phy = cfg->phy[i].addr;
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ddrtr_res->phy_st[i].rank_st[j].ddrtr_data.byte_num = cfg->phy[i].total_byte_num;
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ddrtr_res->phy_st[i].rank_st[j].ddrtr_data.rank_idx = j;
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}
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}
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}
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/* Save ddr training cmd result */
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void ddr_result_data_save(struct ddr_cfg_st *cfg, struct training_data *training)
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{
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unsigned int i;
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unsigned int offset;
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struct training_data *dest = NULL;
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struct ddr_training_result_st *ddrtr_res = (struct ddr_training_result_st *)cfg->res_st;
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if (!ddrtr_res)
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return;
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if (cfg->cur_mode == DDR_MODE_READ)
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dest = &ddrtr_res->phy_st[cfg->phy_idx].rank_st[cfg->rank_idx].ddrtr_data.read;
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else
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dest = &ddrtr_res->phy_st[cfg->phy_idx].rank_st[cfg->rank_idx].ddrtr_data.write;
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if (cfg->phy[cfg->phy_idx].dmc_num == 1)
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ddrtr_memcpy(dest, training, sizeof(struct training_data));
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else {
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/* dmc[0] + dmc[1] */
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offset = cfg->dmc_idx << 4;
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for (i = 0; i < GET_BYTE_NUM(cfg) << 3; i++) {
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dest->ddr_bit_result[i + offset] = training->ddr_bit_result[i + offset];
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dest->ddr_bit_best[i + offset] = training->ddr_bit_best[i + offset];
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}
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dest->ddr_win_sum += training->ddr_win_sum;
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}
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}
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/* Save lpca training data */
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void ddr_lpca_data_save(struct ca_data_st *data)
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{
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#if 0
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unsigned int index;
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struct ddr_training_result_st *result_st
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= (struct ddr_training_result_st *)ddrtr_result;
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struct ddr_training_data_st *tr_data;
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for (index = 0; index < DDR_SUPPORT_PHY_MAX; index++) {
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if (result_st->ddrtr_data[index].base_phy == data->base_phy)
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break;
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}
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tr_data = &result_st->ddrtr_data[index];
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for (index = 0; index < DDR_PHY_CA_MAX; index++)
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tr_data->ca_addr[index] = (data->left[index]
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<< DDR_DATAEYE_RESULT_BIT) | data->right[index];
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#endif
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}
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/* Get DDRT test addrress */
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unsigned int ddr_ddrt_get_test_addr(void)
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{
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if (ddr_training_addr_start <= DDRT_CFG_TEST_ADDR_CMD
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&& ddr_training_addr_end >= DDRT_CFG_TEST_ADDR_CMD) {
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return DDRT_CFG_TEST_ADDR_CMD;
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} else {
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DDR_ERROR("DDRT test address[%x] out of range[%x, %x]",
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DDRT_CFG_TEST_ADDR_CMD,
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ddr_training_addr_start,
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ddr_training_addr_end);
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return ddr_training_addr_start;
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}
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}
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/* Nothing to do in DDR command */
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void ddr_training_suc(void) { return; }
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/* Nothing to do in DDR command */
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void ddr_training_start(void) { return; }
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static void dump_result(struct ddr_training_data_st *ddrtr_data)
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{
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unsigned int i;
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unsigned int base_phy = ddrtr_data->base_phy;
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unsigned int byte_num = ddrtr_data->byte_num;
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unsigned int rank = ddrtr_data->rank_idx;
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unsigned int ACPHYCTL7;
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/* Static register have to read two times to get the right value. */
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ACPHYCTL7 = ddr_read(base_phy + DDR_PHY_ACPHYCTL7);
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ACPHYCTL7 = ddr_read(base_phy + DDR_PHY_ACPHYCTL7);
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for (i = 0; i < ddrtr_data->byte_num << 3; i++) {
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DDR_INFO("Byte[%x] Write[%x][%x] Read[%x][%x]",
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i, ddrtr_data->write.ddr_bit_result[i], ddrtr_data->write.ddr_bit_best[i],
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ddrtr_data->read.ddr_bit_result[i], ddrtr_data->read.ddr_bit_best[i]);
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}
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for (i = 0; i < DDR_PHY_CA_MAX; i++) {
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if (ddrtr_data->ca_addr[i] != 0)
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DDR_INFO("CA[%x] Range[%x]", i, ddrtr_data->ca_addr[i]);
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}
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/* WDQS */
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for (i = 0; i < byte_num; i++) {
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DDR_INFO("[%x = %x] WDQS Byte(%x) ",
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base_phy + DDR_PHY_DXWDQSDLY(rank, i),
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ddr_read(base_phy + DDR_PHY_DXWDQSDLY(rank, i)), i);
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}
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/* WDQ Phase */
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for (i = 0; i < byte_num; i++) {
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DDR_INFO("[%x = %x] WDQ Phase Byte(%x)",
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base_phy + DDR_PHY_DXNWDQDLY(rank, i),
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ddr_read(base_phy + DDR_PHY_DXNWDQDLY(rank, i)), i);
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}
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/* WDQ BDL */
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for (i = 0; i < byte_num; i++) {
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/* DQ0-DQ3 */
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DDR_INFO("[%x = %x] WDQ BDL DQ(%x-%x)",
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base_phy + DDR_PHY_DXNWDQNBDL0(rank, i),
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ddr_read(base_phy + DDR_PHY_DXNWDQNBDL0(rank, i)),
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(i << 3), ((i << 3) + 3));
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/* DQ4-DQ7 */
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DDR_INFO("[%x = %x] WDQ BDL DQ(%x-%x)",
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base_phy + DDR_PHY_DXNWDQNBDL1(rank, i),
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ddr_read(base_phy + DDR_PHY_DXNWDQNBDL1(rank, i)),
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((i << 3) + 4), ((i << 3) + 7));
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}
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/* WDM */
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for (i = 0; i < byte_num; i++) {
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DDR_INFO("[%x = %x] WDM Byte(%x)",
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base_phy + DDR_PHY_DXNWDQNBDL2(rank, i),
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ddr_read(base_phy + DDR_PHY_DXNWDQNBDL2(rank, i)), i);
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}
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/* Write DO/DOS OE */
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for (i = 0; i < byte_num; i++) {
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DDR_INFO("[%x = %x] Write DQ/DQS OE Byte(%x)",
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base_phy + DDR_PHY_DXNOEBDL(rank, i),
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ddr_read(base_phy + DDR_PHY_DXNOEBDL(rank, i)), i);
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}
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/* RDQS */
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for (i = 0; i < byte_num; i++) {
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DDR_INFO("[%x = %x] RDQS Byte(%x)",
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base_phy + DDR_PHY_DXNRDQSDLY(i),
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ddr_read(base_phy + DDR_PHY_DXNRDQSDLY(i)), i);
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}
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/* RDQ BDL */
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for (i = 0; i < byte_num; i++) {
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/* DQ0-DQ3 */
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DDR_INFO("[%x = %x] RDQ BDL DQ(%x-%x)",
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base_phy + DDR_PHY_DXNRDQNBDL0(rank, i),
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ddr_read(base_phy + DDR_PHY_DXNRDQNBDL0(rank, i)),
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(i << 3), ((i << 3) + 3));
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/* DQ4-DQ7 */
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DDR_INFO("[%x = %x] RDQ BDL DQ(%x-%x)",
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base_phy + DDR_PHY_DXNRDQNBDL1(rank, i),
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ddr_read(base_phy + DDR_PHY_DXNRDQNBDL1(rank, i)),
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((i << 3) + 4), ((i << 3) + 7));
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}
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/* Gate */
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for (i = 0; i < byte_num; i++) {
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DDR_INFO("[%x = %x] Gate Byte(%x)",
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base_phy + DDR_PHY_DXNRDQSGDLY(rank, i),
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ddr_read(base_phy + DDR_PHY_DXNRDQSGDLY(rank, i)), i);
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}
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DDR_INFO("[%x = %x] CS",
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base_phy + DDR_PHY_ACCMDBDL2,
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ddr_read(base_phy + DDR_PHY_ACCMDBDL2));
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DDR_INFO("[%x = %x] CLK",
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base_phy + DDR_PHY_ACPHYCTL7, ACPHYCTL7);
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DDR_PHY_SWITCH_RANK(base_phy, rank);
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/* HOST Vref */
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DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num);
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/* DRAM Vref */
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DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num);
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/* Addr Phase */
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DDR_PHY_ADDRPH_DISPLAY_CMD(base_phy);
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/* Addr BDL */
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DDR_PHY_ADDRBDL_DISPLAY_CMD(base_phy);
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/* DCC */
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DDR_PHY_DCC_DISPLAY_CMD(base_phy);
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}
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static void dump_result_by_rank(struct ddr_training_result_st *ddrtr_result,
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unsigned int phy_index, unsigned int rank_index)
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{
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unsigned int mask = 1 << phy_index; /* DDR_BYPASS_PHY0_MASK DDR_BYPASS_PHY1_MASK */
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struct rank_data_st *rank_st = &ddrtr_result->phy_st[phy_index].rank_st[rank_index];
|
||
|
|
|
||
|
|
if (rank_st->item & mask)
|
||
|
|
return;
|
||
|
|
|
||
|
|
DDR_INFO("PHY[%x] RANK[%x]:", phy_index, rank_index);
|
||
|
|
dump_result(&rank_st->ddrtr_data);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void dump_result_by_phy(struct ddr_training_result_st *ddrtr_result,
|
||
|
|
unsigned int phy_index)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
struct phy_data_st *phy_st = &ddrtr_result->phy_st[phy_index];
|
||
|
|
|
||
|
|
for (i = 0; i < phy_st->rank_num; i++) {
|
||
|
|
dump_result_by_rank(ddrtr_result, phy_index, i);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Display ddr training result before return to DDR */
|
||
|
|
static void dump_result_all(struct ddr_training_result_st *ddrtr_result)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
for (i = 0; i < ddrtr_result->phy_num; i++) {
|
||
|
|
dump_result_by_phy(ddrtr_result, i);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int ddr_training_cmd_func(struct ddr_cfg_st *cfg)
|
||
|
|
{
|
||
|
|
int result = 0;
|
||
|
|
struct ddr_cmd_st *cmd_st = (struct ddr_cmd_st *)cfg->cmd_st;
|
||
|
|
unsigned int item = cfg->cur_item;
|
||
|
|
|
||
|
|
DDR_DEBUG("DDR training cmd[%x]", cmd_st->cmd);
|
||
|
|
|
||
|
|
switch (cmd_st->cmd) {
|
||
|
|
case DDR_TRAINING_CMD_SW:
|
||
|
|
/* todo */
|
||
|
|
result = ddr_dataeye_training_func(cfg);
|
||
|
|
result += ddr_vref_training_func(cfg);
|
||
|
|
break;
|
||
|
|
case DDR_TRAINING_CMD_DATAEYE:
|
||
|
|
result = ddr_dataeye_training_func(cfg);
|
||
|
|
break;
|
||
|
|
case DDR_TRAINING_CMD_HW:
|
||
|
|
result = ddr_hw_training_if();
|
||
|
|
break;
|
||
|
|
case DDR_TRAINING_CMD_MPR:
|
||
|
|
result = ddr_mpr_training_func(cfg);
|
||
|
|
break;
|
||
|
|
case DDR_TRAINING_CMD_WL:
|
||
|
|
result = ddr_wl_func(cfg);
|
||
|
|
break;
|
||
|
|
case DDR_TRAINING_CMD_GATE:
|
||
|
|
result = ddr_gating_func(cfg);
|
||
|
|
break;
|
||
|
|
case DDR_TRAINING_CMD_VREF:
|
||
|
|
result = ddr_vref_training_func(cfg);
|
||
|
|
break;
|
||
|
|
case DDR_TRAINING_CMD_AC:
|
||
|
|
result = ddr_ac_training_func(cfg);
|
||
|
|
break;
|
||
|
|
case DDR_TRAINING_CMD_LPCA:
|
||
|
|
result = ddr_lpca_training_func(cfg);
|
||
|
|
break;
|
||
|
|
case DDR_TRAINING_CMD_SW_NO_WL:
|
||
|
|
/* wl bypass */
|
||
|
|
ddr_write(item | DDR_BYPASS_WL_MASK,
|
||
|
|
DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG);
|
||
|
|
result = ddr_dataeye_training_func(cfg);
|
||
|
|
result += ddr_vref_training_func(cfg);
|
||
|
|
/* restore cfg */
|
||
|
|
ddr_write(item,
|
||
|
|
DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG);
|
||
|
|
break;
|
||
|
|
case DDR_TRAINING_CMD_CONSOLE:
|
||
|
|
result = ddr_training_console_if((void *)&ddrt_result_sram);
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
result = -1;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* DDR training command entry. Call by cmd_ddr_handle(). */
|
||
|
|
struct ddr_training_result_st *ddr_training_cmd_entry(
|
||
|
|
struct ddr_cmd_st *cmd_st)
|
||
|
|
{
|
||
|
|
int result = 0;
|
||
|
|
|
||
|
|
struct ddr_cfg_st ddr_cfg;
|
||
|
|
struct ddr_cfg_st *cfg = &ddr_cfg;
|
||
|
|
struct ddr_cmd_st cmd_in_sram;
|
||
|
|
|
||
|
|
ddr_training_addr_start = cmd_st->start;
|
||
|
|
ddr_training_addr_end = cmd_st->start + cmd_st->length;
|
||
|
|
ddr_print_level = cmd_st->level;
|
||
|
|
|
||
|
|
DDR_INFO("DDR Training Version: "DDR_TRAINING_VER);
|
||
|
|
DDR_DEBUG("DDR training command entry. Sysctl[%x = %x]",
|
||
|
|
(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG),
|
||
|
|
ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG));
|
||
|
|
|
||
|
|
#ifdef SYSCTRL_DDR_TRAINING_CFG_SEC
|
||
|
|
DDR_DEBUG("Rank1 Sysctl[%x = %x]",
|
||
|
|
(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC),
|
||
|
|
ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_DDR_TRAINING_CFG_SEC));
|
||
|
|
#endif
|
||
|
|
|
||
|
|
ddr_training_cfg_init(cfg);
|
||
|
|
ddrtr_memcpy(&cmd_in_sram, cmd_st, sizeof(struct ddr_cmd_st));
|
||
|
|
cfg->cmd_st = (void *)&cmd_in_sram;
|
||
|
|
cfg->res_st = (void *)&ddrt_result_sram;
|
||
|
|
|
||
|
|
ddr_training_result_init(cfg, &ddrt_result_sram);
|
||
|
|
|
||
|
|
if (cmd_st->cmd == DDR_TRAINING_CMD_HW)
|
||
|
|
result = ddr_hw_training(cfg);
|
||
|
|
else if (cmd_st->cmd == DDR_TRAINING_CMD_PCODE)
|
||
|
|
result = ddr_pcode_training(cfg);
|
||
|
|
else if (cmd_st->cmd == DDR_TRAINING_CMD_DCC)
|
||
|
|
result = ddr_dcc_training_func(cfg);
|
||
|
|
else if (cmd_st->cmd == DDR_TRAINING_CMD_CONSOLE)
|
||
|
|
result = ddr_training_console_if((void *)&ddrt_result_sram);
|
||
|
|
else
|
||
|
|
result = ddr_training_all(cfg);
|
||
|
|
|
||
|
|
dump_result_all(&ddrt_result_sram);
|
||
|
|
|
||
|
|
if (!result) {
|
||
|
|
return &ddrt_result_sram;
|
||
|
|
} else {
|
||
|
|
DDR_DEBUG("DDR training result[%x]", result);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
}
|