455 lines
16 KiB
C
455 lines
16 KiB
C
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/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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#ifndef DDR_TRAINING_IMPL_H
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#define DDR_TRAINING_IMPL_H
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#ifndef __ASSEMBLY__
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#include "ddr_training_custom.h"
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#include "ddr_training_internal_config.h"
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#include "ddr_interface.h"
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/****** special config define*******************************************/
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#ifdef DDR_DATAEYE_NORMAL_NOT_ADJ_CONFIG
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/* Adjust dataeye window consume a lot of time, disable it will make boot
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* faster.
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* NOTE: The WDQ Phase and RDQS MUST be config a good value in the init table
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* to avoid window trend to one side.
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*/
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#define DDR_DATAEYE_NORMAL_ADJUST (DDR_FALSE)
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#else
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#define DDR_DATAEYE_NORMAL_ADJUST (DDR_TRUE)
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#endif
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/* MUST adjust dataeye window after HW or MPR training */
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#define DDR_DATAEYE_ABNORMAL_ADJUST (DDR_TRUE)
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/****** ddr training item bypass mask define ****************************/
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#define DDR_BYPASS_PHY0_MASK 0x1 /* [0]PHY0 training */
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#define DDR_BYPASS_PHY1_MASK 0x2 /* [1]PHY1 training */
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#define DDR_BYPASS_WL_MASK 0x10 /* [4]Write leveling */
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#define DDR_BYPASS_GATE_MASK 0x100 /* [8]Gate training */
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#define DDR_BYPASS_DATAEYE_MASK 0x10000 /* [16]Dataeye training */
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#define DDR_BYPASS_PCODE_MASK 0x40000 /* [18]Pcode training */
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#define DDR_BYPASS_HW_MASK 0x100000 /* [20]Hardware read training */
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#define DDR_BYPASS_MPR_MASK 0x200000 /* [21]MPR training */
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#define DDR_BYPASS_AC_MASK 0x400000 /* [22]AC training */
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#define DDR_BYPASS_LPCA_MASK 0x800000 /* [23]LPDDR CA training */
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#define DDR_BYPASS_VREF_HOST_MASK 0x1000000 /* [24]Host Vref training */
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#define DDR_BYPASS_VREF_DRAM_MASK 0x2000000 /* [25]DRAM Vref training */
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#define DDR_BYPASS_DCC_MASK 0x08000000 /* [27]DCC training */
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#define DDR_BYPASS_DATAEYE_ADJ_MASK 0x10000000 /* [28]Dataeye adjust */
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#define DDR_BYPASS_WL_ADJ_MASK 0x20000000 /* [29]WL write adjust */
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#define DDR_BYPASS_HW_ADJ_MASK 0x40000000 /* [30]HW read adjust */
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#define DDR_BYPASS_ALL_MASK 0xffffffff /* all bypass */
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/****** ddr read/write define **********************************************/
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unsigned int ddr_read(unsigned addr);
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void ddr_write(unsigned val, unsigned addr);
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/****** common define **********************************************/
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/* special ddrt need special read and write register */
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#ifdef DDR_DDRT_SPECIAL_CONFIG
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#define DDRT_REG_READ(addr) ddr_ddrt_read(addr)
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#define DDRT_REG_WRITE(val, addr) ddr_ddrt_write(val, addr)
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#else
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#define DDRT_REG_READ(addr) ddr_read(addr)
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#define DDRT_REG_WRITE(val, addr) ddr_write(val, addr)
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#endif
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#define DDR_MODE_READ (1 << 0)
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#define DDR_MODE_WRITE (1 << 1)
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#define DDR_ENTER_SREF (1 << 0)
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#define DDR_EXIT_SREF (1 << 1)
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/* DSB to make sure the operation is complete */
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#ifndef DDR_ASM_DSB
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#if (__LINUX_ARM_ARCH__ >= 8)
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#define DDR_ASM_DSB() { __asm__ __volatile__("dsb sy"); }
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#else
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#define DDR_ASM_DSB() { __asm__ __volatile__("dsb"); }
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#endif
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#endif
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#define DDR_HWR_WAIT_TIMEOUT 0xffffffff
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#define DDR_SFC_WAIT_TIMEOUT (1000)
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#define DDR_LPCA_WAIT_TIMEOUT (1000)
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#ifdef CFG_EDA_VERIFY
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#define DDR_AUTO_TIMING_DELAY (1)
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#else
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#define DDR_AUTO_TIMING_DELAY (1000)
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#endif
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#define DDR_FIND_DQ_BOTH (1 << 0) /* find a valid value*/
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/* x is valid, (x-1) is invalid*/
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#define DDR_FIND_DQ_LEFT (1 << 1)
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/* x is valid, (x+1) is invalid*/
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#define DDR_FIND_DQ_RIGHT (1 << 2)
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#define DDR_VREF_DRAM_VAL_MAX (0x32) /* 92.50%*VDDIO */
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#define DDR_VREF_DRAM_VAL_MIN (0x0) /* 60.00%*VDDIO */
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#define DDR_PHY_REG_DQ_NUM 4 /* one register has 4 DQ BDL */
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#define DDR_PHY_CA_MAX 10
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#define DDR_PHY_CA_REG_MAX (DDR_PHY_CA_MAX >> 1)
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#define DDR_TRUE 1
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#define DDR_FALSE 0
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#define DDR_WIN_MIDDLE (1 << 0)
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#define DDR_WIN_LEFT (1 << 1)
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#define DDR_WIN_RIGHT (1 << 2)
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#define DDR_DELAY_PHASE 1
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#define DDR_DELAY_BDL 2
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#ifndef DDR_DATAEYE_WIN_NUM
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/* Dateeye window number. More bigger more slower when Vref training. */
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#define DDR_DATAEYE_WIN_NUM 8
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#endif
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#ifndef DDR_LOOP_TIMES_LMT
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/* Dataeye DQ deskew times for best result. More bigger more slower. */
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#define DDR_LOOP_TIMES_LMT 1
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#endif
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#ifndef DDR_VREF_COMPARE_TIMES
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/* Compare times when find best vref value. More bigger more slower. */
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#define DDR_VREF_COMPARE_TIMES 3
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#endif
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#ifndef DDR_MPR_RDQS_FIND_TIMES
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/* MPR Find first start rdqs times. More bigger, start rdqs more bigger. */
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#define DDR_MPR_RDQS_FIND_TIMES 3
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#endif
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#ifndef DDR_VREF_COMPARE_STEP
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/* Compare step when begin to find. More bigger, more mistake, more stable. */
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#define DDR_VREF_COMPARE_STEP 3
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#endif
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#define DDR_DATAEYE_RESULT_MASK 0xffff
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#define DDR_DATAEYE_RESULT_BIT 16
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#define DDR_WL_BDL_STEP 2 /* wl bdl step */
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#define DDR_GATE_BDL_STEP 2 /* gate bdl step */
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#define DDR_DQS_ADJ_STEP 1 /* WR/RD DQS adjust step */
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#define DDR_DDRT_MODE_GATE (1 << 0)
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#define DDR_DDRT_MODE_DATAEYE (1 << 1)
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#define DDR_CHECK_TYPE_DDRT (1 << 0)
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#define DDR_CHECK_TYPE_MPR (1 << 1)
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#define DDR_MPR_BYTE_MASK 0xff
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#define DDR_MPR_BIT_MASK 0x1
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#define DDR_MPR_BYTE_BIT 16 /* 16 bit (2 byte) */
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#define DDR_PHY_AC_TEST_VAL0 0x0
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#define DDR_PHY_AC_TEST_VAL1 0xffffffff
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#define DDR_PHY_AC_TEST_VAL2 0x55555555
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#define DDR_PHY_AC_TEST_VAL3 0xaaaaaaaa
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/*******log define ***********************************************/
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#if defined(DDR_TRAINING_CMD) && defined(DDR_TRAINING_LOG_CONFIG)
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#define DDR_INFO(fmt...) ddr_training_log(__func__, DDR_LOG_INFO, fmt)
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#define DDR_DEBUG(fmt...) ddr_training_log(__func__, DDR_LOG_DEBUG, fmt)
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#define DDR_WARNING(fmt...) ddr_training_log(__func__, DDR_LOG_WARNING, fmt)
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#define DDR_ERROR(fmt...) ddr_training_log(__func__, DDR_LOG_ERROR, fmt)
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#define DDR_FATAL(fmt...) ddr_training_log(__func__, DDR_LOG_FATAL, fmt)
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#else
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#define DDR_INFO(fmt...)
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#define DDR_DEBUG(fmt...)
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#define DDR_WARNING(fmt...)
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#define DDR_ERROR(fmt...)
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#define DDR_FATAL(fmt...)
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#endif /* DDR_TRAINING_CMD && DDR_TRAINING_LOG_CONFIG */
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/* [11:0] Error type */
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/* 0x00000001 Write Leveling error */
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#define DDR_ERR_WL (1 << 0)
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/* 0x00000002 Hardware Gatining error */
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#define DDR_ERR_HW_GATING (1 << 1)
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/* 0x00000004 Sofeware Gatining error */
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#define DDR_ERR_GATING (1 << 2)
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/* 0x00000008 DDRT test time out */
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#define DDR_ERR_DDRT_TIME_OUT (1 << 3)
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/* 0x00000010 Hardware read dataeye error */
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#define DDR_ERR_HW_RD_DATAEYE (1 << 4)
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/* 0x00000020 MPR error */
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#define DDR_ERR_MPR (1 << 5)
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/* 0x00000040 Dataeye error */
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#define DDR_ERR_DATAEYE (1 << 6)
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/* 0x00000080 LPDDR CA error */
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#define DDR_ERR_LPCA (1 << 7)
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/* [13:12] Error phy */
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/* 0x00001000 PHY0 training error */
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#define DDR_ERR_PHY0 (1 << 12)
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/* 0x00002000 PHY1 training error */
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#define DDR_ERR_PHY1 (1 << 13)
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#define DDR_ERR_BYTE_BIT 24 /* [28:24] Error DQ0-31 */
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#define DDR_ERR_DQ_BIT 20 /* [22:20] Error Byte0-3 */
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/*******data define*********************************************/
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#define GET_BYTE_NUM(cfg) (cfg->phy[cfg->phy_idx].dmc[cfg->dmc_idx].byte_num)
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#ifndef DDR_RELATE_REG_DECLARE
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struct tr_custom_reg {
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};
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#endif
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struct dmc_cfg_sref_st {
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unsigned int val[DDR_DMC_PER_PHY_MAX];
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};
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struct ddr_bdl_st {
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unsigned int bdl[DDR_PHY_BYTE_MAX];
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};
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struct ddr_timing_st {
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unsigned int val[DDR_DMC_PER_PHY_MAX];
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};
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struct rdqs_data_st {
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struct ddr_bdl_st origin;
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struct ddr_bdl_st rank[DDR_RANK_NUM];
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};
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struct ddr_delay_st {
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unsigned int phase[DDR_PHY_BYTE_MAX];
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unsigned int bdl[DDR_PHY_BYTE_MAX];
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};
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struct tr_relate_reg {
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unsigned int auto_ref_timing;
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unsigned int power_down;
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unsigned int dmc_scramb;
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unsigned int dmc_scramb_cfg;
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unsigned int misc_scramb;
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unsigned int ac_phy_ctl;
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unsigned int swapdfibyte_en;
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struct tr_custom_reg custom;
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struct ddr_ddrc_data ddrc;
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};
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struct tr_dq_data {
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unsigned int dq03[DDR_PHY_BYTE_MAX]; /* DQ0-DQ3 BDL */
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unsigned int dq47[DDR_PHY_BYTE_MAX]; /* DQ4-DQ7 BDL */
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unsigned int rdqs[DDR_PHY_BYTE_MAX]; /* RDQS */
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unsigned int rdm[DDR_PHY_BYTE_MAX]; /* RDM */
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unsigned int wdm[DDR_PHY_BYTE_MAX]; /* WDM */
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};
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struct ca_bit_st {
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unsigned int bit_p;
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unsigned int bit_n;
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};
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struct ca_data_st {
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unsigned int base_dmc;
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unsigned int base_phy;
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unsigned int done; /* whether all ca found bdl range */
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unsigned int min; /* min left bound */
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unsigned int max; /* max right bound */
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unsigned def[DDR_PHY_CA_REG_MAX];
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int left[DDR_PHY_CA_MAX];
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int right[DDR_PHY_CA_MAX];
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struct ca_bit_st bits[DDR_PHY_CA_MAX];
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};
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struct ddr_dmc_st {
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unsigned int addr;
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unsigned int byte_num;
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unsigned int ddrt_pattern; /* ddrt reversed data */
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};
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struct ddr_rank_st {
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unsigned int item; /* software training item */
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unsigned int item_hw; /* hardware training item */
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};
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struct ddr_phy_st {
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unsigned int addr;
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unsigned int dram_type;
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unsigned int dmc_num;
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unsigned int rank_num;
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unsigned int total_byte_num;
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struct ddr_dmc_st dmc[DDR_DMC_PER_PHY_MAX];
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struct ddr_rank_st rank[DDR_RANK_NUM];
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};
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struct ddr_cfg_st {
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struct ddr_phy_st phy[DDR_PHY_NUM];
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unsigned int phy_num;
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unsigned int cur_phy; /* current training phy addr */
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unsigned int cur_dmc; /* current training dmc addr */
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unsigned int cur_item; /* current SW or HW training item */
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unsigned int cur_pattern; /* current ddrt pattern */
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unsigned int cur_mode; /* read or write */
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unsigned int cur_byte; /* current training byte index */
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unsigned int cur_dq; /* current training dq index */
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unsigned int phy_idx; /* current training phy index */
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unsigned int rank_idx; /* current training rank index */
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unsigned int dmc_idx; /* current training dmc index */
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unsigned int adjust; /* whether need to adjust dataeye window */
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unsigned int dq_check_type; /* ddrt or mpr */
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void *cmd_st; /* struct ddr_cmd_st */
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void *res_st; /* SW: struct ddr_training_result_st, HW: struct rdqs_data_st */
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};
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struct dcc_ck_st {
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unsigned int val[DDR_CK_RESULT_MAX];
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unsigned int win;
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unsigned int win_min_ctl;
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unsigned int win_max_ctl;
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unsigned int win_min_duty;
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unsigned int win_max_duty;
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unsigned int def_bp;
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unsigned int def_ctl;
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unsigned int def_duty;
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unsigned int idx_duty;
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unsigned int idx_duty_ctl;
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unsigned int idx_ctl;
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unsigned int BYPASS_CK_BIT;
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unsigned int ACIOCTL21_CTL_BIT;
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unsigned int ACIOCTL21_CK_BIT;
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};
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#ifdef DDR_DCC_TRAINING_CONFIG
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struct dcc_data_st {
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struct tr_dq_data rank[DDR_RANK_NUM];
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struct dcc_ck_st ck[DDR_CK_NUM];
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unsigned int item[DDR_CK_NUM];
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unsigned int ioctl21_tmp;
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};
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#endif
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/*******Uart early function ***********************************************/
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#ifndef DDR_PUTS
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#define DDR_PUTS uart_early_puts
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#endif
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#ifndef DDR_PUT_HEX
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#define DDR_PUT_HEX uart_early_put_hex
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#endif
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#ifndef DDR_PUTC
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#define DDR_PUTC uart_early_putc
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#endif
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#if defined(DDR_TRAINING_UART_CONFIG) || defined(DDR_TRAINING_LOG_CONFIG)
|
||
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extern void uart_early_puts(const char *s);
|
||
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extern void uart_early_put_hex(int hex);
|
||
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extern void uart_early_putc(int chr);
|
||
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|
#else
|
||
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#undef DDR_PUTS
|
||
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|
#undef DDR_PUT_HEX
|
||
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|
#undef DDR_PUTC
|
||
|
|
#endif
|
||
|
|
/*******function interface define*********************************************/
|
||
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|
#ifndef DDR_SW_TRAINING_FUNC
|
||
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|
#define DDR_SW_TRAINING_FUNC_PUBLIC
|
||
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#define DDR_SW_TRAINING_FUNC ddr_sw_training_func
|
||
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|
#endif
|
||
|
|
|
||
|
|
#ifndef DDR_HW_TRAINING_FUNC
|
||
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|
#define DDR_HW_TRAINING_FUNC_PUBLIC
|
||
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|
#define DDR_HW_TRAINING_FUNC ddr_hw_training_func
|
||
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|
#endif
|
||
|
|
|
||
|
|
#ifndef DDR_PCODE_TRAINING_FUNC
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||
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|
#define DDR_PCODE_TRAINING_FUNC ddr_pcode_training_func
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifndef DDR_TRAINING_CONSOLE
|
||
|
|
#define DDR_TRAINING_CONSOLE_PUBLIC
|
||
|
|
#define DDR_TRAINING_CONSOLE ddr_training_console
|
||
|
|
#endif
|
||
|
|
/*******Custom function ***********************************************/
|
||
|
|
#ifndef DDR_TRAINING_DDRT_PREPARE_FUNC
|
||
|
|
#define DDR_TRAINING_DDRT_PREPARE_FUNC()
|
||
|
|
#endif
|
||
|
|
#ifndef DDR_TRAINING_SAVE_REG_FUNC
|
||
|
|
#define DDR_TRAINING_SAVE_REG_FUNC(relate_reg, mask)
|
||
|
|
#endif
|
||
|
|
#ifndef DDR_TRAINING_RESTORE_REG_FUNC
|
||
|
|
#define DDR_TRAINING_RESTORE_REG_FUNC(relate_reg)
|
||
|
|
#endif
|
||
|
|
#ifndef ddr_boot_cmd_save_func
|
||
|
|
#define ddr_boot_cmd_save_func(relate_reg) ((void)(relate_reg))
|
||
|
|
#endif
|
||
|
|
#ifndef ddr_boot_cmd_restore_func
|
||
|
|
#define ddr_boot_cmd_restore_func(relate_reg) ((void)(relate_reg))
|
||
|
|
#endif
|
||
|
|
/*******function define*********************************************/
|
||
|
|
int ddr_sw_training_func(void);
|
||
|
|
int ddr_training_boot_func(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_training_cmd_func(struct ddr_cfg_st *cfg);
|
||
|
|
|
||
|
|
void* ddrtr_memset(void *b, int c, unsigned int len);
|
||
|
|
void* ddrtr_memcpy(void *dst, const void *src, unsigned int len);
|
||
|
|
void ddr_training_cfg_init(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_training_by_dmc(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_training_by_rank(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_training_by_phy(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_training_all(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_dataeye_training_func(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_vref_training_func(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_wl_func(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_gating_func(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_ac_training_func(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_lpca_training_func(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_dcc_training_func(struct ddr_cfg_st *cfg);
|
||
|
|
|
||
|
|
void ddr_phy_cfg_update(unsigned int base_phy);
|
||
|
|
void ddr_phy_set_dq_bdl(struct ddr_cfg_st *cfg, unsigned int value);
|
||
|
|
int ddr_hw_training(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_pcode_training(struct ddr_cfg_st *cfg);
|
||
|
|
|
||
|
|
int ddr_mpr_training(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_write_leveling(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_gate_training(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_dataeye_training(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_vref_training(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_ac_training(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_lpca_training(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_dataeye_deskew(struct ddr_cfg_st *cfg, struct training_data *training);
|
||
|
|
void ddr_adjust_dataeye(struct ddr_cfg_st *cfg, struct training_data *training);
|
||
|
|
void ddr_result_data_save(struct ddr_cfg_st *cfg, struct training_data *training);
|
||
|
|
void ddr_lpca_data_save(struct ca_data_st *data);
|
||
|
|
unsigned int ddr_ddrt_get_test_addr(void);
|
||
|
|
int ddr_ddrt_test(unsigned int mask, int byte, int dq);
|
||
|
|
int ddr_dataeye_check_dq(struct ddr_cfg_st *cfg);
|
||
|
|
void ddr_ddrt_init(struct ddr_cfg_st *cfg, unsigned int mode);
|
||
|
|
int ddr_training_check_bypass(struct ddr_cfg_st *cfg, unsigned int mask);
|
||
|
|
int ddr_training_phy_disable(int index);
|
||
|
|
void ddr_training_save_reg(struct ddr_cfg_st *cfg, struct tr_relate_reg *relate_reg,
|
||
|
|
unsigned int mask);
|
||
|
|
void ddr_training_restore_reg(struct ddr_cfg_st *cfg, struct tr_relate_reg *relate_reg);
|
||
|
|
void ddr_training_get_base(int index, unsigned int *base_dmc,
|
||
|
|
unsigned int *base_phy);
|
||
|
|
void ddr_training_switch_axi(struct ddr_cfg_st *cfg);
|
||
|
|
void ddr_training_log(const char *func, int level, const char *fmt, ...);
|
||
|
|
void ddr_training_stat(unsigned int mask, unsigned int phy, int byte, int dq);
|
||
|
|
void ddr_training_error(unsigned int mask, unsigned int phy, int byte, int dq);
|
||
|
|
void ddr_training_start(void);
|
||
|
|
void ddr_training_suc(void);
|
||
|
|
unsigned int ddr_phy_get_byte_num(unsigned int base_dmc);
|
||
|
|
void ddr_training_set_timing(unsigned int base_dmc, unsigned int timing);
|
||
|
|
int ddr_hw_dataeye_read(struct ddr_cfg_st *cfg);
|
||
|
|
|
||
|
|
#ifdef DDR_MPR_TRAINING_CONFIG
|
||
|
|
int ddr_mpr_training_func(struct ddr_cfg_st *cfg);
|
||
|
|
int ddr_mpr_check(struct ddr_cfg_st *cfg);
|
||
|
|
#else
|
||
|
|
static inline int ddr_mpr_training_func(struct ddr_cfg_st *cfg)
|
||
|
|
{
|
||
|
|
DDR_WARNING("Not support DDR MPR training.");
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
static inline int ddr_mpr_check(struct ddr_cfg_st *cfg) { return 0;}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* __ASSEMBLY__ */
|
||
|
|
#endif /* DDR_TRAINING_IMPL_H */
|