192 lines
4.7 KiB
C
Executable File
192 lines
4.7 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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#ifndef __ARM_ARCH_MMU_H
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#define __ARM_ARCH_MMU_H
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#include <linux/types.h>
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#ifdef CONFIG_ARCH_MMU
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/*
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* Translation Table Base Bit Masks
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*/
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#define ARM_TRANSLATION_TABLE_MASK 0xFFFFC000
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/*
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* Domain Access Control Bit Masks
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*/
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#define arm_access_type_no_access(domain_num) (0x0 << (domain_num)*2)
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#define arm_access_type_client(domain_num) (0x1 << (domain_num)*2)
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#define arm_access_type_manager(domain_num) (0x3 << (domain_num)*2)
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#define ARM_MMU_FIRST_LEVEL_FAULT_ID 0x0
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struct arm_mmu_first_level_fault {
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unsigned int id: 2;
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unsigned int sbz: 30;
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};
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#define ARM_MMU_FIRST_LEVEL_PAGE_TABLE_ID 0x1
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struct arm_mmu_first_level_page_table {
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unsigned int id: 2;
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unsigned int sbz0: 1;
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unsigned int ns: 1;
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unsigned int sbz1: 1;
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unsigned int domain: 4;
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unsigned int imp: 1;
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unsigned int base_address: 22;
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};
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#define ARM_MMU_FIRST_LEVEL_SECTION_ID 0x2
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struct arm_mmu_first_level_section {
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unsigned int id: 2;
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unsigned int b: 1;
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unsigned int c: 1;
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unsigned int xn: 1;
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unsigned int domain: 4;
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unsigned int imp: 1;
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unsigned int ap0: 2;
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unsigned int tex: 3;
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unsigned int ap1: 1;
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unsigned int s: 1;
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unsigned int ng: 1;
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unsigned int reserved: 1;
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unsigned int ns: 1;
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unsigned int base_address: 12;
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};
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struct arm_mmu_first_level_reserved {
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unsigned int id: 2;
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unsigned int sbz: 30;
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};
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#define ARM_MMU_SECOND_LEVEL_FAULT_ID 0x0
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struct arm_mmu_second_level_fault {
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unsigned int id: 2;
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unsigned int sbz: 30;
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};
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#define ARM_MMU_SECOND_LEVEL_SMALL_ID 0x2
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struct arm_mmu_second_level_small {
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unsigned int id: 2;
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unsigned int b: 1;
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unsigned int c: 1;
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unsigned int ap0: 2;
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unsigned int tex: 3;
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unsigned int ap1: 1;
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unsigned int s: 1;
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unsigned int ng: 1;
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unsigned int base_address: 20;
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};
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#define ARM_MMU_FIRST_LEVEL_RESERVED_ID 0x3
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#define arm_mmu_first_level_descriptor_address(ttb_base, table_index) \
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(unsigned long *)((unsigned long)(ttb_base) + ((table_index) << 2))
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#define ARM_FIRST_LEVEL_PAGE_TABLE_SIZE 0x4000
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union arm_mmu_first_level_descriptor {
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unsigned long word;
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struct arm_mmu_first_level_fault fault;
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struct arm_mmu_first_level_page_table page_table;
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struct arm_mmu_first_level_section section;
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struct arm_mmu_first_level_reserved reserved;
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};
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union arm_mmu_second_level_descriptor {
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unsigned long word;
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struct arm_mmu_second_level_fault fault;
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struct arm_mmu_second_level_small small;
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};
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static inline void arm_mmu_section(int ttb_base, int actual_base,
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int virtual_base, unsigned int tex, unsigned int cacheable,
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unsigned int bufferable, unsigned int perm,
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unsigned int shareable)
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{
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register union arm_mmu_first_level_descriptor desc;
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desc.word = 0;
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desc.section.id = ARM_MMU_FIRST_LEVEL_SECTION_ID;
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desc.section.c = cacheable;
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desc.section.b = bufferable;
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desc.section.xn = 0;
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desc.section.domain = 0;
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desc.section.ap0 = perm;
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desc.section.tex = tex;
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desc.section.ap1 = 0;
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desc.section.s = shareable;
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desc.section.base_address = actual_base;
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*arm_mmu_first_level_descriptor_address(ttb_base, (virtual_base))
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= desc.word;
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}
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static inline void x_arm_mmu_section(int abase, int vbase, int size,
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unsigned int tex, unsigned int cache, unsigned int buff,
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unsigned int access, unsigned int shareable)
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{
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int i;
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int j = abase;
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int k = vbase;
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unsigned long ttb_base = CONFIG_TTB_ADDR;
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for (i = size; i > 0 ; i--, j++, k++)
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arm_mmu_section(ttb_base, j, k, tex, cache,
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buff, access, shareable);
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}
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#define ARM_UNCACHEABLE 0
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#define ARM_CACHEABLE 1
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#define ARM_UNBUFFERABLE 0
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#define ARM_BUFFERABLE 1
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#define ARM_ACCESS_PERM_NONE_NONE 0
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#define ARM_ACCESS_PERM_RW_NONE 1
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#define ARM_ACCESS_PERM_RW_RO 2
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#define ARM_ACCESS_PERM_RW_RW 3
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#define ARM_NOSHAREABLE 0
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#define ARM_SHAREABLE 1
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#define ARM_MEMTYPE_STRONGORDER 0
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#define ARM_MEMTYPE_DEVICE 1
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#define ARM_MEMTYPE_NORMAL 2
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#define ARM_MEMTYPE_RESERVED 3
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#define ARM_CACHETYPE_NOCACHE 0
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#define ARM_CACHETYPE_WRITEBACK 1
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#define ARM_CACHETYPE_WRITETHROUGH 2
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#define ARM_CACHETYPE_WRITEBACK_ONLY 3
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/*
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* Initialization for the Domain Access Control Register
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*/
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#define ARM_ACCESS_DACR_DEFAULT ( \
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arm_access_type_manager(0) | \
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arm_access_type_no_access(1) | \
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arm_access_type_no_access(2) | \
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arm_access_type_no_access(3) | \
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arm_access_type_no_access(4) | \
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arm_access_type_no_access(5) | \
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arm_access_type_no_access(6) | \
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arm_access_type_no_access(7) | \
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arm_access_type_no_access(8) | \
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arm_access_type_no_access(9) | \
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arm_access_type_no_access(10) | \
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arm_access_type_no_access(11) | \
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arm_access_type_no_access(12) | \
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arm_access_type_no_access(13) | \
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arm_access_type_no_access(14) | \
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arm_access_type_no_access(15))
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#endif
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#endif
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