237 lines
7.9 KiB
C
Executable File
237 lines
7.9 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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#ifndef __CHIP_REGS_H__
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#define __CHIP_REGS_H__
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/* -------------------------------------------------------------------- */
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#define RAM_START_ADRS 0x04010500
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#define STACK_TRAINING 0x0401A000
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/* -------------------------------------------------------------------- */
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#define FMC_REG_BASE 0x10000000
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/* -------------------------------------------------------------------- */
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#define REG_BASE_SF 0x10040000
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/* -------------------------------------------------------------------- */
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#define EMMC_REG_BASE 0x10010000
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#define SDIO1_REG_BASE 0x10020000
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/* -------------------------------------------------------------------- */
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#define USB3_CTRL_REG_BASE 0x10030000
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/* -------------------------------------------------------------------- */
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#define USB_OHCI_BASE 0x10030000
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/* -------------------------------------------------------------------- */
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#define DDRC0_REG_BASE 0x11330000
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/* -------------------------------------------------------------------- */
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#define TIMER0_REG_BASE 0x12000000
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#define TIMER1_REG_BASE 0x12000020
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#define TIMER2_REG_BASE 0x12001000
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#define TIMER3_REG_BASE 0x12001020
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#define REG_TIMER_RELOAD 0x0
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#define REG_TIMER_VALUE 0x4
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#define REG_TIMER_CONTROL 0x8
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#define CFG_TIMER_CLK 3000000
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#define CFG_TIMERBASE TIMER0_REG_BASE
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/* enable timer.32bit, periodic,mask irq, 1 divider. */
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#define CFG_TIMER_CTRL 0xC2
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/* -------------------------------------------------------------------- */
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/* Clock and Reset Generator REG */
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/* -------------------------------------------------------------------- */
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#define CRG_REG_BASE 0x12010000
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#define REG_CRG80 0x0140
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#define REG_CRG81 0x0144
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#define REG_CRG91 0x016c
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#define REG_CRG110 0x01b8
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/* USB 2.0 CRG Control register offset */
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#define REG_USB2_CTRL REG_CRG80
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/* FMC CRG register offset */
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#define REG_FMC_CRG REG_CRG81
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#define FMC_SRST (0x1 << 0)
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#define FMC_CLK_ENABLE (0x1 << 1)
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#define FMC_CLK_SEL_MASK (0x7 << 2)
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#define FMC_CLK_SEL_SHIFT 0x2
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/* SDR/DDR clock */
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#define FMC_CLK_24M 0x0
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#define FMC_CLK_100M 0x1
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#define FMC_CLK_150M 0x2
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#define FMC_CLK_200M 0x3
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/* Only DDR clock */
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#define FMC_CLK_300M 0x4
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#define FMC_CLK_360M 0x5
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#define fmc_clk_sel(_clk) \
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(((_clk) << FMC_CLK_SEL_SHIFT) & FMC_CLK_SEL_MASK)
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#define get_fmc_clk_type(_reg) \
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(((_reg) & FMC_CLK_SEL_MASK) >> FMC_CLK_SEL_SHIFT)
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/* Ethernet CRG register offset */
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#define REG_ETH_CRG REG_CRG91
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#define REG_ETH_MAC_IF 0x8c
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/* Uart CRG register offset */
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#define REG_UART_CRG REG_CRG110
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#define uart_clk_sel(_clk) (((_clk) & 0x3) << 18)
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#define UART_CLK_SEL_MASK (0x3 << 18)
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#define UART_CLK_APB 0
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#define UART_CLK_24M 1
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#define UART_CLK_2M 2
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/* SDIO0 CRG register offset */
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#define REG_SDIO0_CRG (CRG_REG_BASE + 0x238)
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/* eMMC CRG register offset */
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#define REG_EMMC_CRG (CRG_REG_BASE + 0x1f4)
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#define mmc_clk_sel(_clk) (((_clk) & 0x7) << 24)
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#define MMC_CLK_SEL_MASK (0x7 << 24)
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#define get_mmc_clk_type(_reg) (((_reg) >> 24) & 0x7)
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/* -------------------------------------------------------------------- */
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/* System Control REG */
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/* -------------------------------------------------------------------- */
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#define SYS_CTRL_REG_BASE 0x12020000
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#define REG_BASE_SCTL SYS_CTRL_REG_BASE
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#define REG_SC_SYSSTAT 0x8c
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#define spi_input_sle(x) (((x) >> 16) & 0x1)
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/* System Control register offset */
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#define REG_SC_CTRL 0x0000
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#define sc_ctrl_timer0_clk_sel(_clk) (((_clk) & 0x1) << 16)
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#define TIMER0_CLK_SEL_MASK (0x1 << 16)
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#define TIMER_CLK_3M 0
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#define TIMER_CLK_BUS 1
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#define SC_CTRL_REMAP_CLEAR (0x1 << 8)
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/* System soft reset register offset */
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#define REG_SC_SYSRES 0x0004
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/* System Status register offset */
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#define REG_SYSSTAT 0x008c
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/* bit[7]=0: 3-Byte address mode; bit[7]=1: 4-Byte address mode */
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#define get_spi_nor_addr_mode(_reg) (((_reg) >> 7) & 0x1)
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/* bit[6]=0; SPI nor flash; bit[6]=1: SPI nand flash */
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#define get_spi_device_type(_reg) (((_reg) >> 10) & 0x1)
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/* bit[4]=0 SPI; bit[4]=1: EMMC */
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#define get_sys_boot_mode(_reg) (((_reg) >> 4) & 0x1)
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#define BOOT_FROM_SPI 0
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#define BOOT_FROM_SPI_NAND 1
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#define BOOT_FROM_NAND 2
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#define BOOT_FROM_EMMC 1
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#define NF_BOOTBW_MASK (1 << 11)
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#define REG_SC_GEN5 0x0134
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#define REG_SC_GEN0 0x0138
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#define REG_SC_GEN1 0x013c
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#define REG_SC_GEN2 0x0140
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#define REG_SC_GEN3 0x0144
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#define REG_SC_GEN4 0x0148
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#define REG_SC_GEN9 0x0154
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/********** Communication Register and flag used by bootrom *************/
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#define REG_START_FLAG (SYS_CTRL_REG_BASE + REG_SC_GEN1)
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#define START_MAGIC 0x444f574e
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#define SELF_BOOT_TYPE_USBDEV 0x2 /* debug */
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/* -------------------------------------------------------------------- */
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/* Peripheral Control REG */
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/* -------------------------------------------------------------------- */
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#define MISC_REG_BASE 0x12028000
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#define MISC_CTRL17 0x0044
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#define MISC_CTRL18 0x48
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#define MISC_CTRL7 0x001C
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#define MISC_CTRL8 0x0020
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#define MISC_CTRL9 0x0024
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#define EMMC_ISO_EN (0x1 << 16)
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#define RG_EMMC_LHEN_IN (0x3f << 17)
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/* USB 2.0 MISC Control register offset */
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#define REG_USB2_CTRL0 MISC_CTRL7
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/* base on needs #define REG_USB2_CTRL1 MISC_CTRL9 */
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/* FEPHY Control register offset */
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#define REG_FEPHY_CTRL0 MISC_CTRL8
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#define REG_FEPHY_CTRL1 MISC_CTRL9
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/* -------------------------------------------------------------------- */
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#define IO_CONFIG_REG_BASE 0x12050000
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/* -------------------------------------------------------------------- */
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#define UART0_REG_BASE 0x12040000
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#define UART1_REG_BASE 0x12041000
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#define UART2_REG_BASE 0x12042000
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/* -------------------------------------------------------------------- */
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#define GPIO0_REG_BASE 0x120B0000
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#define GPIO1_REG_BASE 0x120B1000
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#define GPIO2_REG_BASE 0x120B2000
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#define GPIO3_REG_BASE 0x120B3000
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#define GPIO4_REG_BASE 0x120B4000
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#define GPIO5_REG_BASE 0x120B5000
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#define GPIO6_REG_BASE 0x120B6000
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#define GPIO7_REG_BASE 0x120B7000
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#define GPIO8_REG_BASE 0x120B8000
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#define GPIO9_REG_BASE 0x120B9000
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#define FMC_MEM_BASE 0x14000000
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#define FMC_TEXT_ADRS FMC_MEM_BASE
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#define DDR_MEM_BASE 0x40000000
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#define HW_DEC_INTR 86
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/*-----------------------------------------------------------------------
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* EMMC / SD
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* ----------------------------------------------------------------------*/
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/* SDIO0 REG */
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#define SDIO0_BASE_REG 0x10010000
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/* EMMC REG */
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#define EMMC_BASE_REG 0x10010000
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#define REG_BASE_PERI_CTRL REG_BASE_SCTL
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#define REG_BASE_IO_CONFIG IO_CONFIG_REG_BASE
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#define MMC_IOMUX_START_ADDR 0xF8
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#define MMC_IOMUX_END_ADDR 0x13C
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#define MMC_IOMUX_CTRL_MASK (1<<0 | 1<<1)
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#define MMC_IOMUX_CTRL (1<<1)
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#define SYSCNT_REG_BASE 0x12050000
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#define SYSCNT_ENABLE_REG 0x0
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#define SYSCNT_FREQ_REG 0x20
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#define SYSCNT_FREQ 50000000
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#define REG_BASE_SYSCNT SYSCNT_REG_BASE
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#define CNTCR 0x0
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#define CNTFID0 0x20
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/* ---------------------------------------------------------*/
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#define NUM_0 0
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#define NUM_1 1
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#define NUM_2 2
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#define NUM_3 3
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#define NUM_4 4
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#define NUM_5 5
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#define NUM_6 6
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#define NUM_7 7
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#define NUM_8 8
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#define NUM_9 9
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#endif /* End of __CHIP_REGS_H__ */
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