255 lines
7.0 KiB
C
Executable File
255 lines
7.0 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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/*
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* Send set/get features command to SPI Nand flash
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*/
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/*****************************************************************************/
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void spi_nand_set_cmd(struct fmc_host *host, u_char op, u_char addr,
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u_char val)
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{
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unsigned int reg;
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reg = fmc_cmd_cmd1(op ? SPI_CMD_SET_FEATURE : SPI_CMD_GET_FEATURES);
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fmc_write(host, FMC_CMD, reg);
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fmc_pr(FT_DBG, "\t||||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
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fmc_write(host, FMC_ADDRL, addr);
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fmc_pr(FT_DBG, "\t||||-Set ADDRL[%#x]%#x\n", FMC_ADDRL, addr);
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reg = op_cfg_fm_cs(host->cmd_op.cs) | OP_CFG_OEN_EN |
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op_cfg_addr_num(FEATURES_OP_ADDR_NUM);
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fmc_write(host, FMC_OP_CFG, reg);
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fmc_pr(FT_DBG, "\t||||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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reg = fmc_data_num_cnt(FEATURES_DATA_LEN);
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fmc_write(host, FMC_DATA_NUM, reg);
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fmc_pr(FT_DBG, "\t||||-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
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reg = fmc_op_cmd1_en(ENABLE) | fmc_op_addr_en(ENABLE) |
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FMC_OP_REG_OP_START;
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if (op == SET_OP) {
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reg |= fmc_op_write_data_en(ENABLE);
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writeb(val, host->iobase);
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fmc_pr(FT_DBG, "\t||||-Write IO[%p]%#x\n", host->iobase,
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*(u_char *)host->iobase);
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} else {
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reg |= fmc_op_read_data_en(ENABLE);
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}
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fmc_write(host, FMC_OP, reg);
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fmc_pr(FT_DBG, "\t||||-Set OP[%#x]%#x\n", FMC_OP, reg);
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fmc_cmd_wait_cpu_finish(host);
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}
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/*****************************************************************************/
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unsigned char spi_nand_feature_op(struct fmc_spi *spi, unsigned char op,
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unsigned char addr, unsigned char val)
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{
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unsigned int reg = 0;
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const char *str[] = {"Get", "Set"};
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struct fmc_host *host = (struct fmc_host *)spi->host;
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if ((op == GET_OP) && (addr == STATUS_ADDR)) {
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fmc_pr(SR_DBG, "\n\t\t|*-Start Get Status\n");
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reg = op_cfg_fm_cs(host->cmd_op.cs) | OP_CFG_OEN_EN;
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fmc_write(host, FMC_OP_CFG, reg);
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fmc_pr(SR_DBG, "\t\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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reg = fmc_op_read_status_en(ENABLE) | FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, reg);
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fmc_pr(SR_DBG, "\t\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
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fmc_cmd_wait_cpu_finish(host);
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val = fmc_read(host, FMC_STATUS);
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fmc_pr(SR_DBG, "\t\t|*-End Get Status, result: %#x\n", val);
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return val;
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}
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fmc_pr(FT_DBG, "\t|||*-Start %s feature, addr[%#x]\n", str[op], addr);
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fmc100_ecc0_switch(host, ENABLE);
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spi_nand_set_cmd(host, op, addr, val);
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if (op == GET_OP) {
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val = readb(host->iobase);
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fmc_pr(FT_DBG, "\t||||-Read IO[%p]%#x\n", host->iobase,
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*(u_char *)host->iobase);
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}
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fmc100_ecc0_switch(host, DISABLE);
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fmc_pr(FT_DBG, "\t|||*-End %s Feature[%#x]:%#x\n", str[op], addr, val);
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return val;
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}
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/*****************************************************************************/
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/*
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* Read status[C0H]:[0]bit OIP, judge whether the device is busy or not
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*/
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static int spi_general_wait_ready(struct fmc_spi *spi)
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{
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unsigned char status;
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/* just get a big number, so move left 12 bits */
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unsigned int deadline = 1 << 12;
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struct fmc_host *host = (struct fmc_host *)spi->host;
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do {
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status = spi_nand_feature_op(spi, GET_OP, STATUS_ADDR, 0);
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if (!(status & STATUS_OIP_MASK)) {
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if ((host->cmd_op.l_cmd == NAND_CMD_ERASE2) &&
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(status & STATUS_E_FAIL_MASK)) {
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return status;
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}
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if ((host->cmd_op.l_cmd == NAND_CMD_PAGEPROG) &&
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(status & STATUS_P_FAIL_MASK)) {
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return status;
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}
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return 0;
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}
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udelay(1); /* delay 1 us */
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} while (deadline--);
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db_msg("Error: SPI Nand wait ready timeout, status: %#x\n", status);
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return 1;
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}
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/*****************************************************************************/
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/*
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* Send write enable cmd to SPI Nand, status[C0H]:[2]bit WEL must be set 1
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*/
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static int spi_general_write_enable(struct fmc_spi *spi)
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{
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unsigned int reg;
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struct fmc_host *host = (struct fmc_host *)spi->host;
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if (WE_DBG)
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printf("\n");
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fmc_pr(WE_DBG, "\t|*-Start Write Enable\n");
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reg = spi_nand_feature_op(spi, GET_OP, STATUS_ADDR, 0);
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if (reg & STATUS_WEL_MASK) {
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fmc_pr(WE_DBG, "\t||-Write Enable was opened! reg: %#x\n",
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reg);
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return 0;
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}
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reg = fmc_read(host, FMC_GLOBAL_CFG);
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fmc_pr(WE_DBG, "\t||-Get GLOBAL_CFG[%#x]%#x\n", FMC_GLOBAL_CFG, reg);
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if (reg & FMC_GLOBAL_CFG_WP_ENABLE) {
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reg &= ~FMC_GLOBAL_CFG_WP_ENABLE;
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fmc_write(host, FMC_GLOBAL_CFG, reg);
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fmc_pr(WE_DBG, "\t||-Set GLOBAL_CFG[%#x]%#x\n",
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FMC_GLOBAL_CFG, reg);
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}
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reg = fmc_cmd_cmd1(SPI_CMD_WREN);
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fmc_write(host, FMC_CMD, reg);
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fmc_pr(WE_DBG, "\t||-Set CMD[%#x]%#x\n", FMC_CMD, reg);
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reg = op_cfg_fm_cs(host->cmd_op.cs) | OP_CFG_OEN_EN;
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fmc_write(host, FMC_OP_CFG, reg);
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fmc_pr(WE_DBG, "\t||-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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reg = fmc_op_cmd1_en(ENABLE) | FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, reg);
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fmc_pr(WE_DBG, "\t||-Set OP[%#x]%#x\n", FMC_OP, reg);
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fmc_cmd_wait_cpu_finish(host);
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#if WE_DBG
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spi->driver->wait_ready(spi);
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reg = spi_nand_feature_op(spi, GET_OP, STATUS_ADDR, 0);
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if (reg & STATUS_WEL_MASK) {
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fmc_pr(WE_DBG, "\t||-Write Enable success. reg: %#x\n", reg);
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} else {
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db_msg("Error: Write Enable failed! reg: %#x\n", reg);
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return reg;
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}
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#endif
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fmc_pr(WE_DBG, "\t|*-End Write Enable\n");
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return 0;
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}
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/*****************************************************************************/
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/*
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* judge whether SPI Nand support QUAD read/write or not
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*/
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static int spi_is_quad(struct fmc_spi *spi)
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{
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const char *if_str[] = {"STD", "DUAL", "DIO", "QUAD", "QIO"};
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fmc_pr(QE_DBG, "\t\t|||*-SPI read iftype: %s write iftype: %s\n",
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if_str[spi->read->iftype], if_str[spi->write->iftype]);
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if ((spi->read->iftype == IF_TYPE_QUAD) ||
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(spi->read->iftype == IF_TYPE_QIO) ||
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(spi->write->iftype == IF_TYPE_QUAD) ||
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(spi->write->iftype == IF_TYPE_QIO))
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return 1;
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return 0;
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}
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/*****************************************************************************/
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/*
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* Send set features cmd to SPI Nand, feature[B0H]:[0]bit QE would be set
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*/
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static int spi_general_qe_enable(struct fmc_spi *spi)
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{
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unsigned int reg;
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unsigned int op;
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const char *str[] = {"Disable", "Enable"};
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fmc_pr(QE_DBG, "\t||*-Start SPI Nand flash QE\n");
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op = spi_is_quad(spi);
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fmc_pr(QE_DBG, "\t|||*-End Quad check, SPI Nand %s Quad.\n", str[op]);
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reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
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fmc_pr(QE_DBG, "\t|||-Get [%#x]feature: %#x\n", FEATURE_ADDR, reg);
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if ((reg & FEATURE_QE_ENABLE) == op) {
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fmc_pr(QE_DBG, "\t||*-SPI Nand quad was %sd!\n", str[op]);
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return op;
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}
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if (op == ENABLE)
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reg |= FEATURE_QE_ENABLE;
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else
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reg &= ~FEATURE_QE_ENABLE;
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spi_nand_feature_op(spi, SET_OP, FEATURE_ADDR, reg);
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fmc_pr(QE_DBG, "\t|||-SPI Nand %s Quad\n", str[op]);
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spi->driver->wait_ready(spi);
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reg = spi_nand_feature_op(spi, GET_OP, FEATURE_ADDR, 0);
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if ((reg & FEATURE_QE_ENABLE) == op)
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fmc_pr(QE_DBG, "\t|||-SPI Nand %s Quad succeed!\n", str[op]);
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else
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db_msg("Error: %s Quad failed! reg: %#x\n", str[op], reg);
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fmc_pr(QE_DBG, "\t||*-End SPI Nand %s Quad.\n", str[op]);
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return op;
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}
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/****************************************************************************/
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/* some spi nand flash don't QUAD enable */
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static int spi_do_not_qe_enable(struct fmc_spi *spi)
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{
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return 0;
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} |