145 lines
4.2 KiB
C
Executable File
145 lines
4.2 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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#ifndef DDR_INTERFACE_H
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#define DDR_INTERFACE_H
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#define DDR_PHY_BYTE_MAX 4
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#define DDR_PHY_BIT_NUM 8
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/* support max bit 32*/
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#define DDR_PHY_BIT_MAX (DDR_PHY_BYTE_MAX * DDR_PHY_BIT_NUM)
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#define DDR_REG_NAME_MAX 32 /* register name */
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#define DDR_CA_ADDR_MAX 10
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#define DDR_SUPPORT_PHY_MAX 2 /* support max phy number */
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#define DDR_SUPPORT_RANK_MAX 2 /* support max rank number */
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#define DDR_SUPPORT_DMC_MAX 4 /* support max dmc number */
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#define DDR_CK_RESULT_MAX 2 /* DCC CK result number */
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/**
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* DDR training register number:
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* WDQS 4
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* WDQ Phase 4
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* WDQ BDL 8
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* WDM 4
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* Write DQ/DQS OE 4
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* RDQS 4
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* RDQ BDL 8
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* Gate 4
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* CS 1
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* CLK 1
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* Host Vref 4
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* DRAM Vref 4
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* CA Phase 1
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* CA BDL 5
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* -------------------
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* 60
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*/
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#define DDR_TRAINING_REG_NUM 60
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/* register max. */
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#define DDR_TRAINING_REG_MAX (DDR_TRAINING_REG_NUM * DDR_SUPPORT_PHY_MAX)
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#define DDR_TRAINING_CMD_SW (1 << 0)
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#define DDR_TRAINING_CMD_HW (1 << 1)
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#define DDR_TRAINING_CMD_MPR (1 << 2)
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#define DDR_TRAINING_CMD_WL (1 << 3)
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#define DDR_TRAINING_CMD_GATE (1 << 4)
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#define DDR_TRAINING_CMD_DATAEYE (1 << 5)
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#define DDR_TRAINING_CMD_VREF (1 << 6)
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#define DDR_TRAINING_CMD_AC (1 << 7)
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#define DDR_TRAINING_CMD_LPCA (1 << 8)
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#define DDR_TRAINING_CMD_SW_NO_WL (1 << 9)
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#define DDR_TRAINING_CMD_CONSOLE (1 << 10)
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#define DDR_TRAINING_CMD_DCC (1 << 11)
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#define DDR_TRAINING_CMD_PCODE (1 << 12)
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/*******log level ********************/
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#define DDR_LOG_INFO_STR "info"
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#define DDR_LOG_DEBUG_STR "debug"
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#define DDR_LOG_WARNING_STR "warning"
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#define DDR_LOG_ERROR_STR "error"
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#define DDR_LOG_FATAL_STR "fatal"
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#define DDR_LOG_INFO (1 << 0)
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#define DDR_LOG_DEBUG (1 << 1)
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#define DDR_LOG_WARNING (1 << 2)
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#define DDR_LOG_ERROR (1 << 3)
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#define DDR_LOG_FATAL (1 << 4)
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#define DDR_TRAINING_BOOT_RESULT_ADDR (TEXT_BASE + 0x1000000) /* boot + 16M */
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#define DDR_TRAINING_VER "V2.1.6 20181228"
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#define DDR_VERSION 0x216
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struct training_data {
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unsigned int ddr_bit_result[DDR_PHY_BIT_MAX];
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unsigned int ddr_bit_best[DDR_PHY_BIT_MAX];
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unsigned int ddr_win_sum;
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};
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struct ddr_training_data_st {
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unsigned int base_phy;
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unsigned int byte_num;
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unsigned int rank_idx;
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struct training_data read;
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struct training_data write;
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unsigned int ca_addr[DDR_CA_ADDR_MAX];
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};
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struct rank_data_st {
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unsigned int item;
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struct ddr_training_data_st ddrtr_data;
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};
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struct phy_data_st {
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unsigned int rank_num;
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struct rank_data_st rank_st[DDR_SUPPORT_RANK_MAX];
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};
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struct ddr_training_result_st {
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unsigned int phy_num;
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struct phy_data_st phy_st[DDR_SUPPORT_PHY_MAX];
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};
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struct ddr_reg_val_st {
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unsigned int rank_index;
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unsigned int byte_index;
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unsigned int offset;
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unsigned int val;
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char name[DDR_REG_NAME_MAX];
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};
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struct ddr_cmd_st {
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unsigned int cmd;
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unsigned int level;
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unsigned int start;
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unsigned int length;
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};
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typedef struct ddr_training_result_st * (*ddr_cmd_entry_func)
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(struct ddr_cmd_st *cmd_st);
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/* DDR training interface before boot */
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int ddr_pcode_training_if(void);
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int ddr_sw_training_if(void);
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int ddr_hw_training_if(void);
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int ddr_training_console_if(void *args);
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/* DDR training check interface when boot */
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struct ddr_training_result_st *ddr_cmd_training_if(struct ddr_cmd_st *cmd_st);
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int check_ddr_training(void);
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/* DDR training command interface after boot */
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void ddr_reg_result_display(struct ddr_training_result_st *ddrtr_result);
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void ddr_cmd_result_display(struct ddr_training_result_st *ddrtr_result,
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unsigned int cmd);
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void *ddr_cmd_get_entry(void);
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void ddr_cmd_prepare_copy(void);
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void ddr_cmd_site_save(void);
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void ddr_cmd_site_restore(void);
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#endif /* DDR_INTERFACE_H */
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