380 lines
10 KiB
C
Executable File
380 lines
10 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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/*
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Get status/config register value from SPI Nor flash
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*/
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unsigned char spi_general_get_flash_register(struct fmc_spi *spi, u_char cmd)
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{
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unsigned char status;
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unsigned int reg;
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struct fmc_host *host = (struct fmc_host *)spi->host;
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host->set_system_clock(NULL, ENABLE);
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fmc_pr(SR_DBG, "\t * Start get flash Register[%#x]\n", cmd);
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reg = op_cfg_fm_cs(spi->chipselect) | OP_CFG_OEN_EN;
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fmc_write(host, FMC_OP_CFG, reg);
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if (cmd == SPI_CMD_RDSR) {
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reg = fmc_op_read_status_en(ENABLE) | FMC_OP_REG_OP_START;
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goto cmd_config_done;
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}
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fmc_write(host, FMC_CMD, cmd);
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fmc_pr(SR_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, cmd);
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reg = fmc_data_num_cnt(SPI_NOR_CR_LEN);
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fmc_write(host, FMC_DATA_NUM, reg);
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fmc_pr(SR_DBG, "\t Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
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reg = fmc_op_cmd1_en(ENABLE) | fmc_op_read_data_en(ENABLE) |
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FMC_OP_REG_OP_START;
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cmd_config_done:
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fmc_write(host, FMC_OP, reg);
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fmc_pr(SR_DBG, "\t Set OP[%#x]%#x\n", FMC_OP, reg);
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fmc_cmd_wait_cpu_finish(host);
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if (cmd == SPI_CMD_RDSR)
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status = fmc_read(host, FMC_STATUS);
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else
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status = readb(host->iobase);
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fmc_pr(SR_DBG, "\t * End get flash Register[%#x], val: %#x\n", cmd,
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status);
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return status;
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}
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/*****************************************************************************/
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/*
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Read status[C0H]:[0]bit OIP, judge whether the device is busy or not
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*/
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static int spi_general_wait_ready(struct fmc_spi *spi)
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{
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unsigned char status;
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/* need a big number,so move left 20 bit */
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unsigned int deadline = 1 << 20;
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do {
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status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
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if (!(status & SPI_NOR_SR_WIP_MASK))
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return 0;
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udelay(1); /* delay 1 us */
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} while (deadline--);
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db_msg("Error: SPI nor wait ready timeout, status[%#x]\n", status);
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return 1;
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}
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/*****************************************************************************/
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/*
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Send write enable cmd to SPI Nor, status[C0H]:[2]bit WEL must be set 1
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*/
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static int spi_general_write_enable(struct fmc_spi *spi)
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{
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unsigned char status;
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unsigned int reg;
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struct fmc_host *host = (struct fmc_host *)spi->host;
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if (WE_DBG)
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printf("\n");
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fmc_pr(WE_DBG, "\t * Start Write Enable\n");
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status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
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fmc_pr(WE_DBG, "\t Read Status Register[%#x]:%#x\n", SPI_CMD_RDSR,
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status);
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if (status & STATUS_WEL_MASK) {
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fmc_pr(WE_DBG, "\t Write Enable was opened! reg: %#x\n",
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status);
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return 0;
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}
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reg = fmc_read(host, FMC_GLOBAL_CFG);
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if (reg & FMC_GLOBAL_CFG_WP_ENABLE) {
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reg &= ~FMC_GLOBAL_CFG_WP_ENABLE;
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fmc_write(host, FMC_GLOBAL_CFG, reg);
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fmc_pr(WE_DBG, "\t Set GLOBAL_CFG[%#x]%#x\n",
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FMC_GLOBAL_CFG, reg);
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}
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reg = fmc_cmd_cmd1(SPI_CMD_WREN);
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fmc_write(host, FMC_CMD, reg);
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fmc_pr(WE_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, reg);
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reg = op_cfg_fm_cs(spi->chipselect) | OP_CFG_OEN_EN;
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fmc_write(host, FMC_OP_CFG, reg);
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fmc_pr(WE_DBG, "\t Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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reg = fmc_op_cmd1_en(ENABLE) | FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, reg);
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fmc_pr(WE_DBG, "\t Set OP[%#x]%#x\n", FMC_OP, reg);
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fmc_cmd_wait_cpu_finish(host);
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spi->driver->wait_ready(spi);
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reg = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
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if (reg & STATUS_WEL_MASK) {
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fmc_pr(WE_DBG, "\t Write Enable success.reg: %#x\n", reg);
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} else {
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db_msg("Error: Write Enable failed! status: %#x\n", reg);
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return status;
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}
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fmc_pr(WE_DBG, "\t * End Write Enable\n");
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return 0;
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}
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/*****************************************************************************/
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/*
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enable 4byte address for SPI which memory more than 16M
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*/
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static int spi_general_entry_4addr(struct fmc_spi *spi, int enable)
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{
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unsigned char status;
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unsigned int reg;
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const char *str[] = {"Disable", "Enable"};
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struct fmc_host *host = (struct fmc_host *)spi->host;
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fmc_pr(AC_DBG, "\t* Start SPI Nor flash %s 4-byte mode.\n",
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str[enable]);
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if (spi->addrcycle != SPI_NOR_4BYTE_ADDR_LEN) {
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fmc_pr(AC_DBG, "\t* Flash isn't support entry 4-byte mode.\n");
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return 0;
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}
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status = spi_general_get_flash_register(spi, SPI_CMD_RDSR3);
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fmc_pr(AC_DBG, "\t Read Status Register-3[%#x]:%#x\n", SPI_CMD_RDSR3,
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status);
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if (spi_nor_get_4byte_by_cr(status) == enable) {
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fmc_pr(AC_DBG, "\t* 4-byte was %sd, reg:%#x\n", str[enable],
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status);
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return 0;
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}
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if (enable)
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reg = SPI_CMD_EN4B;
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else
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reg = SPI_CMD_EX4B;
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fmc_write(host, FMC_CMD, fmc_cmd_cmd1(reg));
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fmc_pr(AC_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, reg);
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reg = op_cfg_fm_cs(spi->chipselect) | OP_CFG_OEN_EN;
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fmc_write(host, FMC_OP_CFG, reg);
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fmc_pr(AC_DBG, "\t Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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reg = fmc_op_cmd1_en(ENABLE) | FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, reg);
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fmc_pr(AC_DBG, "\t Set OP[%#x]%#x\n", FMC_OP, reg);
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fmc_cmd_wait_cpu_finish(host);
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spi->driver->wait_ready(spi);
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status = spi_general_get_flash_register(spi, SPI_CMD_RDSR3);
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fmc_pr(AC_DBG, "\t Read SR-3[%#x]:%#x\n", SPI_CMD_RDSR3,
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status);
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if (spi_nor_get_4byte_by_cr(status) != enable) {
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db_msg("Error: %s 4-byte failed! SR3:%#x\n",
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str[enable], status);
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return status;
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}
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fmc_pr(AC_DBG, "\t %s 4-byte success, SR3:%#x\n", str[enable], status);
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fmc_pr(AC_DBG, "\t* End SPI Nor flash %s 4-byte mode.\n", str[enable]);
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return 0;
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}
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/****************************************************************************/
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/*
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judge whether SPI Nor support QUAD read write or not
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*/
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int spi_is_quad(struct fmc_spi *spi)
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{
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char *const if_str[] = {"STD", "DUAL", "DIO", "QUAD", "QIO", "DTR"};
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fmc_pr(QE_DBG, "\t\t|*-SPI read iftype: %s write iftype: %s\n",
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if_str[spi->read->iftype], if_str[spi->write->iftype]);
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if ((spi->read->iftype == IF_TYPE_QUAD) ||
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(spi->read->iftype == IF_TYPE_QIO) ||
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(spi->write->iftype == IF_TYPE_QUAD) ||
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#ifdef CONFIG_DTR_MODE_SUPPORT
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(spi->read->iftype == IF_TYPE_DTR) ||
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#endif
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(spi->write->iftype == IF_TYPE_QIO)
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) {
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return 1;
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}
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return 0;
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}
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/*****************************************************************************/
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static void spi_general_set_cmd(struct fmc_spi *spi)
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{
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unsigned int reg;
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struct fmc_host *host = (struct fmc_host *)spi->host;
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reg = fmc_cmd_cmd1(SPI_CMD_WRSR);
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fmc_write(host, FMC_CMD, reg);
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fmc_pr(QE_DBG, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, reg);
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reg = op_cfg_fm_cs(spi->chipselect) | OP_CFG_OEN_EN;
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fmc_write(host, FMC_OP_CFG, reg);
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fmc_pr(QE_DBG, "\t|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, reg);
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reg = fmc_data_num_cnt(SPI_NOR_SR_LEN + SPI_NOR_CR_LEN);
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fmc_write(host, FMC_DATA_NUM, reg);
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fmc_pr(QE_DBG, "\t|-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, reg);
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reg = fmc_op_cmd1_en(ENABLE) |
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fmc_op_write_data_en(ENABLE) |
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FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, reg);
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fmc_pr(QE_DBG, "\t|-Set OP[%#x]%#x\n", FMC_OP, reg);
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fmc_cmd_wait_cpu_finish(host);
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}
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/*****************************************************************************/
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/*
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* enable QE bit if QUAD read write is supported by SPI
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*/
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static int spi_general_qe_enable(struct fmc_spi *spi)
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{
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unsigned char status;
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unsigned char config;
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unsigned char op;
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const char *str[] = {"Disable", "Enable"};
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struct fmc_host *host = (struct fmc_host *)spi->host;
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op = spi_is_quad(spi);
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fmc_pr(QE_DBG, "\t*-Start SPI Nor %s Quad.\n", str[op]);
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config = spi_general_get_flash_register(spi, SPI_CMD_RDCR);
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fmc_pr(QE_DBG, "\t|-Read Config Register[%#x]%#x\n", SPI_CMD_RDCR,
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config);
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if (op == spi_nor_get_qe_by_cr(config)) {
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fmc_pr(QE_DBG, "\t* Quad was %sd, config:%#x\n", str[op],
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config);
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return op;
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}
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status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
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fmc_pr(QE_DBG, "\t|-Read Status Register[%#x]%#x\n", SPI_CMD_RDSR,
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status);
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spi->driver->write_enable(spi);
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if (op)
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config |= SPI_NOR_CR_QE_MASK;
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else
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config &= ~SPI_NOR_CR_QE_MASK;
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writeb(status, host->iobase);
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writeb(config, host->iobase + SPI_NOR_SR_LEN);
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fmc_pr(QE_DBG, "\t|-Write IO[%p]%#x\n", host->iobase,
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*(unsigned short *)host->iobase);
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spi_general_set_cmd(spi);
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spi->driver->wait_ready(spi);
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config = spi_general_get_flash_register(spi, SPI_CMD_RDCR);
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if (op == spi_nor_get_qe_by_cr(config)) {
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fmc_pr(QE_DBG, "\t|-%s Quad success, config: %#x\n", str[op],
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config);
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} else {
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db_msg("Error: %s Quad failed! reg: %#x\n", str[op], config);
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}
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fmc_pr(QE_DBG, "\t* End SPI Nor %s Quad.\n", str[op]);
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return op;
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}
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/*****************************************************************************/
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/*
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some chip don't QUAD enable
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*/
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static int spi_do_not_qe_enable(struct fmc_spi *spi)
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{
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return 0;
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}
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/*****************************************************************************/
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/*
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* some chip set the mux HOLD#/RESET#/IO3 pin to RESET#, as it is HOLD# default.
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*/
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static void spi_nor_reset_pin_enable(struct fmc_spi *spi, int enable)
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{
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unsigned char config;
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unsigned int regval;
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const char *str[] = {"HOLD#", "RESET#"};
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struct fmc_host *host = (struct fmc_host *)spi->host;
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config = spi_general_get_flash_register(spi, SPI_CMD_RDSR3);
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fmc_pr(RST_DB, "\t|-Read SR-3[%#x], val: %#x\n",
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SPI_CMD_RDSR3, config);
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if (enable == spi_nor_get_rst_hold_by_cr(config)) {
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fmc_pr(RST_DB, " Device has worked on %s.\n", str[enable]);
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return;
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}
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fmc_pr(RST_DB, " Start to enable %s function.\n", str[enable]);
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spi->driver->write_enable(spi);
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if (enable)
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config = spi_nor_set_rst_by_cr(config);
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else
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config = spi_nor_set_hold_by_cr(config);
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writeb(config, host->iobase);
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fmc_pr(RST_DB, "\t|-Write IO[%p]%#x\n", host->iobase,
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*(unsigned char *)host->iobase);
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regval = fmc_cmd_cmd1(SPI_CMD_WRSR3);
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fmc_write(host, FMC_CMD, regval);
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fmc_pr(RST_DB, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, regval);
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regval = op_cfg_fm_cs(spi->chipselect) | OP_CFG_OEN_EN;
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fmc_write(host, FMC_OP_CFG, regval);
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fmc_pr(RST_DB, "\t|-Set OP_CFG[%#x]%#x\n",
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FMC_OP_CFG, regval);
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regval = fmc_data_num_cnt(SPI_NOR_CR_LEN);
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fmc_write(host, FMC_DATA_NUM, regval);
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fmc_pr(RST_DB, "\t|-Set DATA_NUM[%#x]%#x\n",
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FMC_DATA_NUM, regval);
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regval = fmc_op_cmd1_en(ENABLE) |
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fmc_op_write_data_en(ENABLE) |
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FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, regval);
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fmc_pr(RST_DB, "\t|-Set OP[%#x]%#x\n", FMC_OP, regval);
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fmc_cmd_wait_cpu_finish(host);
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spi->driver->wait_ready(spi);
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config = spi_general_get_flash_register(spi, SPI_CMD_RDSR3);
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fmc_pr(RST_DB, "\t|-Read SR-3[%#x], val: %#x\n",
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SPI_CMD_RDSR3, config);
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if (enable == spi_nor_get_rst_hold_by_cr(config))
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fmc_pr(RST_DB, "\t|- Set the MUX pin to RESET# success!\n");
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else
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fmc_pr(RST_DB, "\t|- The MUX pin works on HOLD# or DNU!\n");
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}
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