103 lines
3.2 KiB
C
Executable File
103 lines
3.2 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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/*****************************************************************************/
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/* SpanSion SPI Nor Flash "S25FL256S" Bank Address Register command */
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#define SS_SPI_CMD_BRRD 0x16 /* Read Bank Register */
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#define SS_SPI_CMD_BRWR 0x17 /* Write Bank Register */
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/* Bank Address Register length(byte) */
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#define SS_SPI_NOR_BR_LEN 1
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/* Extended Address Enable bit[7] include in Bank Address Register */
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#define SS_SPI_NOR_BR_EAE_SHIFT 7
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#define SS_SPI_NOR_BR_EAE_MASK (1 << SS_SPI_NOR_BR_EAE_SHIFT)
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#define ss_spi_nor_get_eae_by_br(br) (((br) & SS_SPI_NOR_BR_EAE_MASK) \
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>> SS_SPI_NOR_BR_EAE_SHIFT)
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/*****************************************************************************/
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static void spi_s25fl256s_set_cmd(struct fmc_spi *spi)
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{
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unsigned int regval;
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struct fmc_host *host = (struct fmc_host *)spi->host;
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regval = fmc_cmd_cmd1(SS_SPI_CMD_BRWR);
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fmc_write(host, FMC_CMD, regval);
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fmc_pr(AC_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, regval);
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regval = op_cfg_fm_cs(spi->chipselect);
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fmc_write(host, FMC_OP_CFG, regval);
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fmc_pr(AC_DBG, "\t Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, regval);
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regval = fmc_data_num_cnt(SS_SPI_NOR_BR_LEN);
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fmc_write(host, FMC_DATA_NUM, regval);
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fmc_pr(AC_DBG, "\t Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, regval);
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regval = fmc_op_cmd1_en(ENABLE)
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| fmc_op_write_data_en(ENABLE)
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| FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, regval);
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fmc_pr(AC_DBG, "\t Set OP[%#x]%#x\n", FMC_OP, regval);
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fmc_cmd_wait_cpu_finish(host);
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}
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/*****************************************************************************/
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/*
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enable 4byte address mode for SpanSion "s25fl256" SPI Nor
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*/
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static int spi_s25fl256s_entry_4addr(struct fmc_spi *spi, int enable)
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{
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unsigned char bank;
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const char *str[] = {"Disable", "Enable"};
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struct fmc_host *host = (struct fmc_host *)spi->host;
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fmc_pr(AC_DBG, "\t* Start SpanSion SPI Nor %s 4-byte mode.\n",
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str[enable]);
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if (spi->addrcycle != SPI_NOR_4BYTE_ADDR_LEN) {
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fmc_pr(AC_DBG, "\t* Flash isn't support 4-byte mode.\n");
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return 0;
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}
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/* Read old Bank Register value */
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bank = spi_general_get_flash_register(spi, SS_SPI_CMD_BRRD);
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fmc_pr(AC_DBG, "\t Read Bank Register[%#x]%#x\n", SS_SPI_CMD_BRRD,
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bank);
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if (ss_spi_nor_get_eae_by_br(bank) == enable) {
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fmc_pr(AC_DBG, "\t* 4-byte was %sd, bank:%#x\n", str[enable],
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bank);
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return 0;
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}
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/* Write new Bank Register value */
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if (enable)
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bank |= SS_SPI_NOR_BR_EAE_MASK;
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else
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bank &= ~SS_SPI_NOR_BR_EAE_MASK;
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writeb(bank, host->iobase);
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fmc_pr(AC_DBG, "\t Write IO[%p]%#x\n", host->iobase,
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*(unsigned char *)host->iobase);
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spi_s25fl256s_set_cmd(spi);
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spi->driver->wait_ready(spi);
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/* Check out Bank Register value */
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bank = spi_general_get_flash_register(spi, SS_SPI_CMD_BRRD);
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fmc_pr(AC_DBG, "\t Read Bank Register[%#x]%#x\n", SS_SPI_CMD_BRRD,
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bank);
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if (ss_spi_nor_get_eae_by_br(bank) != enable) {
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db_msg("Error: %s 4bytes failed! bank: %#x\n", str[enable],
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bank);
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return bank;
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}
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fmc_pr(AC_DBG, "\t %s 4byte success, bank:%#x.\n", str[enable], bank);
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fmc_pr(AC_DBG, "\t* End SpanSion SPI Nor %s 4-byte mode.\n",
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str[enable]);
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return 0;
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}
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