91 lines
2.7 KiB
C
Executable File
91 lines
2.7 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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/*****************************************************************************/
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#define XTX_READ_SR_H 0x35
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#define XTX_READ_SR_L 0x05
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/****************************************************************************/
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static void spi_xtx_set_op(struct fmc_spi *spi)
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{
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unsigned int regval;
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struct fmc_host *host = (struct fmc_host *)spi->host;
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regval = fmc_cmd_cmd1(SPI_CMD_WRSR);
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fmc_write(host, FMC_CMD, regval);
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fmc_pr(QE_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, regval);
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regval = op_cfg_fm_cs(spi->chipselect) | OP_CFG_OEN_EN;
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fmc_write(host, FMC_OP_CFG, regval);
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fmc_pr(QE_DBG, "\t Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, regval);
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regval = fmc_data_num_cnt(sizeof(unsigned short));
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fmc_write(host, FMC_DATA_NUM, regval);
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fmc_pr(QE_DBG, "\t Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, regval);
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regval = fmc_op_cmd1_en(ENABLE) | fmc_op_write_data_en(ENABLE) |
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FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, regval);
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fmc_pr(QE_DBG, "\t Set OP[%#x]%#x\n", FMC_OP, regval);
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fmc_cmd_wait_cpu_finish(host);
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}
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/****************************************************************************/
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/*
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enable QE bit if QUAD read write is supported by xtx's flash
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*/
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static int spi_xtx_qe_enable(struct fmc_spi *spi)
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{
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unsigned char status_h;
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unsigned char status_l;
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unsigned char op;
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unsigned short reg;
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const char *str[] = {"Disable", "Enable"};
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struct fmc_host *host = (struct fmc_host *)spi->host;
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op = spi_is_quad(spi);
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fmc_pr(QE_DBG, "\t* Start SPI Nor xtx %s Quad.\n", str[op]);
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status_h = spi_general_get_flash_register(spi, XTX_READ_SR_H);
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fmc_pr(QE_DBG, "\t Read Status Register-h[%#x]%#x\n", XTX_READ_SR_H,
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status_h);
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if (op == spi_nor_get_qe_by_cr(status_h)) {
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fmc_pr(QE_DBG, "\t* Quad was %s status:%#x\n", str[op], status_h);
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goto QE_END;
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}
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spi->driver->write_enable(spi);
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status_l = spi_general_get_flash_register(spi, XTX_READ_SR_L);
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if (op)
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status_h |= SPI_NOR_CR_QE_MASK;
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else
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status_h &= ~SPI_NOR_CR_QE_MASK;
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/* Move left to 8 bit to assign a value to the upper bits */
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reg = ((unsigned short)status_h << 8) | status_l;
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writew(reg, host->iobase);
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fmc_pr(QE_DBG, "\t Write IO[%p]%#x\n", host->iobase,
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*(unsigned short *)host->iobase);
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spi_xtx_set_op(spi);
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/* wait the flash have switched quad mode success */
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spi->driver->wait_ready(spi);
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status_h = spi_general_get_flash_register(spi, XTX_READ_SR_H);
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fmc_pr(QE_DBG, "\t Read Status Register-h[%#x]:%#x\n",
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XTX_READ_SR_H, status_h);
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if (op == spi_nor_get_qe_by_cr(status_h)) {
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fmc_pr(QE_DBG, "\t %s Quad success. status_h:%#x\n",
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str[op], status_h);
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} else {
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db_msg("Error: %s Quad failed! reg:%#x\n", str[op],
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status_h);
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}
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QE_END:
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return status_h;
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}
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