89 lines
3.3 KiB
C
Executable File
89 lines
3.3 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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/* register offset address */
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/* base address: DDR_REG_BASE_DDRT */
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#define DDRT_OP 0x0 /* DDRT operation config */
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#define DDRT_STATUS 0x4 /* DDRT status indicating */
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#define DDRT_BURST_CONFIG 0x8 /* DDRT burst transfer config */
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#define DDRT_MEM_CONFIG 0xc /* DDRT SDRAM config */
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#define DDRT_BURST_NUM 0x10 /* DDRT burst number config */
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/* DDRT burst number config register while testing address */
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#define DDRT_ADDR_NUM 0x14
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#define DDRT_LOOP_NUM 0x18 /* DDRT loop number config */
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/* This register specified the system DDR starting address */
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#define DDRT_DDR_BASE_ADDR 0x1c
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#define DDRT_ADDR 0x20 /* DDRT test start address config */
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#define DDRT_REVERSED_DQ 0x30 /* DDRT reversed DQ indicating */
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#define DDRT_SEED 0x38 /* DDRT starting random seed */
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#define DDRT_KDATA 0x3c /* DDRT kdata config */
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#define DDRT_DATA0 0x40 /* DDRT PRBS7 data config register0 */
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#define DDRT_DATA1 0x44 /* DDRT PRBS7 data config register1 */
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#define DDRT_DATA2 0x48 /* DDRT PRBS7 data config register2 */
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#define DDRT_DATA3 0x4c /* DDRT PRBS7 data config register3 */
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/* DQ3~DQ0 error number indicator, every 8bit for each DQ */
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#define DDRT_DQ_ERR_CNT(n) (0x60 + ((n) << 2))
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/* DQ31~DQ0 error number overflow indicator, every bit for each DQ. */
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#define DDRT_DQ_ERR_OVFL 0x80
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/* register mask */
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#define DDRT_TEST_MODE_MASK 0x300 /* DDRT Test Mode */
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#define DDRT_TEST_DONE_MASK 0x1 /* [0] DDRT operation finish signal.*/
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/* [1] DDRT Test result indicator. No error occurred, test pass. */
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#define DDRT_TEST_PASS_MASK 0x2
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/* register bit */
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#define DDRT_DDR_MEM_WIDTH 12 /* SDRAM total width */
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/* register value */
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#define DDRT_CFG_START 0x1
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#define DDRT_CFG_BURST_CFG_DATAEYE 0x4f
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#define DDRT_CFG_BURST_CFG_GATE 0x43
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#ifdef CFG_EDA_VERIFY
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#define DDRT_CFG_BURST_NUM 0x5 /* ddrt test number */
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#else
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#define DDRT_CFG_BURST_NUM 0x7f /* ddrt test number */
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#endif
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#define DDRT_CFG_SEED 0x6d6d6d6d
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#define DDRT_CFG_REVERSED 0x55aa55aa
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#ifndef DDRT_CFG_BASE_ADDR
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/* [CUSTOM] DDR training start address. MEM_BASE_DDR */
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#define DDRT_CFG_BASE_ADDR 0x0
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#endif
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/* [CUSTOM] DDRT test address. 0x800000 = 8M */
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#define DDRT_CFG_TEST_ADDR_CMD (DDRT_CFG_BASE_ADDR + 0x800000)
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/* [CUSTOM] DDRT test start address. */
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#define DDRT_CFG_TEST_ADDR_BOOT DDRT_CFG_BASE_ADDR
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#define DDRT_CFG_ADDR_NUM 0xffffffff
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#define DDRT_CFG_LOOP_NUM 0x0
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/* [2:0]000:8 bit; 001:9 bit; 010:10 bit; 011:11 bit; 100:12 bit.
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single SDRAM column number.*/
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#define DDRT_DDR_COL_WIDTH 0x2
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/* [6:4]000:11 bit; 001:12 bit; 010:13 bit; 011:14 bit; 100:15 bit; 101:16 bit.
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single SDRAM row number */
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#define DDRT_DDR_ROW_WIDTH 0x50
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/* [8]0:4 Bank; 1:8 Bank. single SDRAM bank number */
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#define DDRT_DDR_BANK_WIDTH 0x100
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#define DDRT_WR_COMPRARE_MODE (0<<8) /* Write read & compare mode */
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#define DDRT_WRITE_ONLY_MODE (1<<8) /* Write only mode */
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#define DDRT_READ_ONLY_MODE (2<<8) /* Read only mode */
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#define DDRT_RANDOM_WR_MODE (3<<8) /* Random write & read mode */
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#define DDRT_PATTERM_PRBS9 (0<<12)
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#define DDRT_PATTERM_PRBS7 (1<<12)
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#define DDRT_PATTERM_PRBS11 (2<<12)
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#define DDRT_PATTERM_K28_5 (3<<12)
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/* other */
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#define DDRT_WAIT_TIMEOUT (1000000)
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#define DDRT_READ_TIMEOUT (20)
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#define DDRT_PCODE_WAIT_TIMEOUT (100000)
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/* DDRT test DDR using space */
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#define DDRT_GET_TEST_ADDR(addr) ((addr)>>1)
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