459 lines
19 KiB
C
Executable File
459 lines
19 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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/* register offset address */
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/* base address: DDR_REG_BASE_PHY0 DDR_REG_BASE_PHY1 */
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/* control the initialization of the PHY */
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#define DDR_PHY_PHYINITCTRL 0x4
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#define DDR_PHY_PHYINITSTATUS 0x8 /* Read Data Eye Calibration Error*/
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#define DDR_PHY_IMPSTATUS 0x28 /* This register specify the ZQ calibration result. */
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#define DDR_PHY_DRAMCFG 0x2c /* DRAM config register */
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#define DDR_PHY_TRAINCTRL0 0x48 /* hw training control */
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#define DDR_PHY_MODEREG01 0x64 /* Extend Mode Register 01 */
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#define DDR_PHY_MODEREG23 0x68 /* Extend Mode Register 23 */
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/* update delay setting in registers to PHY */
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#define DDR_PHY_MISC 0x70
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#define DDR_PHY_DMSEL 0x84 /* DM Swap Selection */
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#define DDR_PHY_SWTMODE 0xa0 /* S/W training mode */
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/* issue one DQS pulse from PHY to DRAM */
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#define DDR_PHY_SWTWLDQS 0xa4
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#define DDR_PHY_SWTRLT 0xa8 /* S/W training result*/
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/* Host vref. [5:0]range [17:12]refsel */
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#define DDR_PHY_PHYRSCTRL 0xB0 /* PHY Register Slice Contrl */
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#define DDR_PHY_IOCTL2 0xB4
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#define DDR_PHY_VREFTCTRL 0xc0 /* VREF Training Control Register. */
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#define DDR_PHY_DVRFTCTRL 0xC4 /* DRAM VREF Training */
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#define DDR_PHY_ACADDRBDL(n) (0x140 + ((n) << 2))
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#define DDR_PHY_IMP_CTRL1 0x170 /* AC/DX ZQ selection */
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#define DDR_PHY_IMP_STATUS1 0x174 /* AC ZCAL status */
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#define DDR_PHY_CATSWAPINDEX 0x01B8 /* CA SWAP index register */
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#define DDR_PHY_CATSWAPSEL 0x01BC /* CA SWAP select register*/
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#define DDR_PHY_CATCONFIG 0x1C8 /* CA Training Configuration */
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#define DDR_PHY_PHYDQRESULT 0x1D0 /* SW CA Training DQ result from PHY */
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#define DDR_PHY_ADDRPHBOUND 0x1D4 /* CA Training addr phase boundary */
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#define DDR_PHY_SWCATPATTERN_P 0x1D8 /* pattern for positive CK edge */
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#define DDR_PHY_SWCATPATTERN_N 0x1DC /* pattern for negative CK edge */
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/* AC command bit delay line setting */
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#define DDR_PHY_ACCMDBDL2 0x128
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/* WR DQ0-DQ3 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line
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on write path */
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#define DDR_PHY_DXNWDQNBDL0(m, n) (0x210 + ((m) << 10) + ((n) << 7))
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/* WR DQ4-DQ7 [6:0] [14:8] [22:16] [30:24] */
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#define DDR_PHY_DXNWDQNBDL1(m, n) (0x214 + ((m) << 10) + ((n) << 7))
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/* WR DM [6:0] the delay value of the bit delay line on DQM */
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#define DDR_PHY_DXNWDQNBDL2(m, n) (0x218 + ((m) << 10) + ((n) << 7))
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/* RD DQ0-DQ3 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line
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on read path */
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#define DDR_PHY_DXNRDQNBDL0(m, n) (0x21C + ((m) << 10) + ((n) << 7))
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/* RD DQ4-DQ7 [6:0] [14:8] [22:16] [30:24] delay value of the bit delay line
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on read path */
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#define DDR_PHY_DXNRDQNBDL1(m, n) (0x220 + ((m) << 10) + ((n) << 7))
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/* [6:0]RD DM*/
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#define DDR_PHY_DXNRDQNBDL2(m, n) (0x224 + ((m) << 10) + ((n) << 7))
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/* [CUSTOM] */
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#define DDR_PHY_DXNOEBDL(m, n) (0x228 + ((m) << 10) + ((n) << 7))
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/* [8:0] rdqs_bdl [24:16]rdqs_cyc.
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phase shift of the Read DQS to create 90 degree delays*/
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#define DDR_PHY_DXNRDQSDLY(n) (0x22C + ((n) << 7))
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/* [6:0] the delay value of delay applied on WDQS for write leveling */
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#define DDR_PHY_DXWDQSDLY(m, n) (0x230 + ((m) << 10) + ((n) << 7))
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/* WR DQ phase BIT 12:8 */
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#define DDR_PHY_DXNWDQDLY(m, n) (0x234 + ((m) << 10) + ((n) << 7))
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/* [CUSTOM] rddqs gating*/
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#define DDR_PHY_DXNRDQSGDLY(m, n) (0x240 + ((m) << 10) + ((n) << 7))
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/* read boundary right 8:0 left 24:16 */
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#define DDR_PHY_DXNRDBOUND(n) (0x250 + ((n) << 7))
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/* write boundary right 4:0 left 20:16 */
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#define DDR_PHY_DXNWDBOUND(n) (0x254 + ((n) << 7))
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/* [5:0] DRAM VREF(DQ) training result */
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#define DDR_PHY_DVREFT_STATUS(n) (0x270 + ((n) << 7))
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/* [4:0] Host PHY VREF(DQ) training result */
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#define DDR_PHY_HVREFT_STATUS(m, n) (0x274 + ((m) << 10) + ((n) << 7))
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/* DDRPHY AC static register */
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#define DDR_PHY_CORNER_DETECTOR 0x104C /* cfg of corner detector */
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#define DDR_PHY_ACPHYCTL4 0x1064 /* AC block PHY control register*/
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#define DDR_PHY_ACPHYCTL7 0x1070
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#define DDR_VREF_HOST_VAL_MAX (0x1f) /* 78.75%*VDDIO */
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#define DDR_VREF_HOST_VAL_MIN (0x0) /* 40.00%*VDDIO */
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/* register mask */
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#define PHY_BDL_MASK 0x7f /* [6:0] */
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#define PHY_WDQS_PHASE_MASK 0xf /* [11:8] */
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#define PHY_RDQS_BDL_MASK 0x1ff /* [CUSTOM] [8:0] rdqsbdl*/
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#define PHY_RDQSG_PHASE_MASK 0x3f /* [14:9] rdqsgphase */
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#define PHY_RDM_BDL_MASK 0x7f /* [6:0] */
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/* hardware gate training result */
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#define PHY_INITSTATUS_GT_MASK 0x20
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#define PHY_SWTRLT_WL_MASK 0xf
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#define PHY_SWTRLT_GATE_MASK 0xf
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#define PHY_WDQ_PHASE_MASK 0x1f
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#define PHY_PHYINITCTRL_MASK 0x1 /* [15:0] all stat */
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/* Read Data Eye Calibration Error */
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#define PHY_PHYINITSTATUS_RDET_ERR 0x100
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#define PHY_ACPHY_DCLK_MASK 0x7 /* cp1p_dclk0 mask */
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#define PHY_ACPHY_DRAMCLK_MASK 0x1 /* halft_dramclk0 mask */
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#define PHY_VRFTRES_DVREF_MASK 0x3f /* [5:0] */
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#define PHY_VRFTRES_HVREF_MASK 0x1f /* [4:0] */
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#define PHY_VRFTRES_RXDIFFCAL_MASK 0xf /* [24:21] */
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#define PHY_ADDRPH_MASK 0x1f /* [20:16] */
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#define PHY_ACADDR_BDL_MASK 0x7f /* [6:0] */
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#define PHY_CATSWAPSEL_BIT_MASK 0xff
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#define PHY_CAT_PATTERN_MASK 0x3ff
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#define PHY_TRAINCTRL0_MASK 0xf /* [3:0] */
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#define PHY_DRAMCFG_TYPE_MASK 0xf /* [3:0] */
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#define PHY_OSC_START_MASK 0x1 /* [0] */
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#define PHY_OSC_RPT_VLD_MASK 0x1 /* [15] */
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#define PHY_OSC_CNT_RDATA_MASK 0xffff /* [31:16] */
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#define PHY_ZCODE_PDRV_MASK 0x3f /* [21:16] */
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#define PHY_ACCTL_PDRV_LATCH_MASK 0x3f /* [29:24] */
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/* register bit */
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#define PHY_MISC_UPDATE_BIT 19 /* [CUSTOM] delay config update bit */
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#define PHY_PHYCONN_RST_BIT 15 /* issue reset signal to PHY counter */
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#define PHY_RDQSG_PHASE_BIT 9 /* [CUSTOM] */
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#define PHY_RDQSG_TX_BDL_BIT 16 /* [22:16] rdqsgtxbdl */
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#define PHY_WDQS_PHASE_BIT 8
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#define PHY_WDQS_BDL_BIT 0
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#define PHY_WDQ_PHASE_BIT 8
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#define PHY_WDM_BDL_BIT 0
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/* [22:16] Write DQS Output Enable Delay Control */
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#define PHY_WDQSOE_BDL_BIT 16
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#define PHY_OEN_BDL_BIT 0
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/* Mode Register 1. Defines the MR3/MR9 of the mode register */
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#define PHY_MODEREG01_MR1_BIT 16
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/* Bit delay line setting of CS1 */
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#define PHY_ACCMD_CS0_BIT 0
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#define PHY_ACCMD_CS1_BIT 16
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#define PHY_ACPHY_DCLK0_BIT 6 /* [8:6] cp1p_dclk0 */
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#define PHY_ACPHY_DCLK1_BIT 9 /* [11:9] ck2p_dclk1 */
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#define PHY_ACPHY_DRAMCLK0_BIT 25 /* [25] halft_dramclk0 */
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#define PHY_ACPHY_DRAMCLK1_BIT 24 /* [24] halft_dramclk1 */
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#define PHY_ACPHY_DRAMCLK_EXT_BIT 3 /* [3] halft_dramclk0 */
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#define PHY_SWTMODE_SW_GTMODE_BIT 1 /* [1] SW gate training */
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#define PHY_ACADDRBDL_ADDR1_BIT 16 /* [16] ADDR1 delay line */
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#define PHY_VREFS_MRS_ENTER_BIT 31 /* [31] */
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#define PHY_OSC_RPT_VLD 15 /* [15] */
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#define PHY_OSC_CNT_RDATA_BIT 16 /* [31:16] */
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#define PHY_ZCODE_PDRV_BIT 16 /* [21:16] */
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#define PHY_ACCTL_PDRV_LATCH_BIT 24 /* [29:24] */
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#define PHY_AC_VDDQ_CAL_EN_BIT 8 /* [8] AC ZQ calibration enable */
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#define PHY_CFG_RX_AGE_COMPST_EN_BIT 31 /* Enable rdqs age compensation function */
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/* BDL register bit */
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#define PHY_BDL_DQ_BIT 0
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#define PHY_BDL_DQ0_BIT 0
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#define PHY_BDL_DQ1_BIT 8
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#define PHY_BDL_DQ2_BIT 16
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#define PHY_BDL_DQ3_BIT 24
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#define PHY_RDM_BDL_BIT 0
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#define PHY_RDQS_BDL_BIT 0
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/* value */
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#define PHY_PHYINITCTRL_DVREFT_SYNC 0x40000 /* DRAM VREF Synchronize */
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/* hw training item defined in PHYINITCTRL */
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#define PHY_PHYINITCTRL_CTL_CKE_BYPASS (1 << 31) /* PACK's CKE bypass function enable. */
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#define PHY_PHYINITCTRL_PIC_PHYUPD_REQ (1 << 30) /* PACK's DFI PHY UPDATAE request by SW. */
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#define PHY_PHYINITCTRL_PIC_TDQSST (1 << 28) /* TDQSS training Enable. */
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#define PHY_PHYINITCTRL_CFG_LPBK_COMPST_EN (1 << 27) /* RDQS/CK loopback delay compensate enable. */
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#define PHY_PHYINITCTRL_PIC_REFRET_SFT (1 << 26) /* Update delay line(switch op_sel) during tRFC. */
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#define PHY_PHYINITCTRL_PIC_REFRET_WR (1 << 25) /* Retraining with MPC write during tRFC. */
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#define PHY_PHYINITCTRL_PIC_REFRET_RD (1 << 24) /* Retraining with MPC read during tRFC. */
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#define PHY_PHYINITCTRL_JTMT_EN (1 << 23) /* PLL Jitter Meter Enable. */
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#define PHY_PHYINITCTRL_CST_EN (1 << 22) /* HW CS Traninig Enable. */
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#define PHY_PHYINITCTRL_ACDVREFS_EN (1 << 21) /* DRAM VREF(AC) Synchronize Operations. */
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#define PHY_PHYINITCTRL_ACHVREFT_EN (1 << 20) /* Host VREF(AC) Training Enable. */
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#define PHY_PHYINITCTRL_ACDVREFT_EN (1 << 19) /* DRAM VREF(AC) Training Enable. */
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#define PHY_PHYINITCTRL_DXDVREFS_EN (1 << 18) /* DRAM VREF(DQ) Synchronize Operations. */
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#define PHY_PHYINITCTRL_HVREFT_EN (1 << 17) /* Host VREF(DQ) Training Enable. */
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#define PHY_PHYINITCTRL_DVREFT_EN (1 << 16) /* DRAM VREF(DQ) Training Enable. */
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#define PHY_PHYINITCTRL_PHYCONN_RST (1 << 15) /* PHY Counter Reset. */
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#define PHY_PHYINITCTRL_PACK_RST (1 << 14) /* PACK Reset. */
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#define PHY_PHYINITCTRL_PHY_RST (1 << 13) /* PHY Reset. */
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#define PHY_PHYINITCTRL_DRAM_RST (1 << 12) /* DRAM Reset. */
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#define PHY_PHYINITCTRL_CAT_EN (1 << 11) /* HW CA Traninig Enable. */
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#define PHY_PHYINITCTRL_DRAM_INIT_EN (1 << 10) /* DRAM Initialization Enable. */
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#define PHY_PHYINITCTRL_WDET_EN (1 << 9) /* Write Data Eye Training Enable. */
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#define PHY_PHYINITCTRL_RDET_EN (1 << 8) /* Read Data Eye Training Enable. */
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#define PHY_PHYINITCTRL_WL2_EN (1 << 7) /* Second Write Leveling Enable. */
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#define PHY_PHYINITCTRL_GDST_EN (1 << 6) /* PHY Read Data Latch Train Enable. */
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#define PHY_PHYINITCTRL_GT_EN (1 << 5) /* Gate Training Enable. */
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#define PHY_PHYINITCTRL_WL_EN (1 << 4) /* Write Leveling Enable. */
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#define PHY_PHYINITCTRL_ZCAL_EN (1 << 3) /* Impedance Calibration Enable. */
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#define PHY_PHYINITCTRL_DLYMEAS_EN (1 << 2) /* Delay Measurement Enable. */
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#define PHY_PHYINITCTRL_PLL_INIT_EN (1 << 1) /* PLL Initialization Enable. */
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#define PHY_PHYINITCTRL_INIT_EN (1 << 0) /* PHY Initialization Enable. */
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#define PHY_HW_GP_PHY_RESET (PHY_PHYINITCTRL_PHY_RST)
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#define PHY_HW_GP_CNT_RESET_START (PHY_PHYINITCTRL_PHYCONN_RST)
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#define PHY_HW_GP_PLL (PHY_PHYINITCTRL_PLL_INIT_EN | PHY_PHYINITCTRL_ZCAL_EN | PHY_PHYINITCTRL_DLYMEAS_EN)
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#define PHY_HW_GP_DRAM_RESET (PHY_PHYINITCTRL_DRAM_RST | PHY_PHYINITCTRL_DRAM_INIT_EN)
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#define PHY_HW_GP_VREF_AC (PHY_PHYINITCTRL_ACDVREFS_EN)
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#define PHY_HW_GP_CS (PHY_PHYINITCTRL_CST_EN)
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#define PHY_HW_GP_VREF_DQ (PHY_PHYINITCTRL_DVREFT_SYNC)
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#define PHY_HW_GP_NORMAL (PHY_PHYINITCTRL_WL_EN \
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| PHY_PHYINITCTRL_GT_EN \
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| PHY_PHYINITCTRL_GDST_EN \
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| PHY_PHYINITCTRL_WL2_EN \
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| PHY_PHYINITCTRL_RDET_EN \
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| PHY_PHYINITCTRL_WDET_EN \
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| PHY_PHYINITCTRL_DVREFT_EN \
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| PHY_PHYINITCTRL_HVREFT_EN \
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| PHY_PHYINITCTRL_PIC_TDQSST)
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#define PHY_HW_GP_CNT_RESET_END (PHY_PHYINITCTRL_PHYCONN_RST)
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/* RDQS range[0, 0x7f], middle value is 0x40, but it affected by
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temperature, so middle value change to 0x30 */
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#define PHY_RDQS_MIDDLE_VAL 0x30
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/* DQ range[0, 0x7f], middle value is 0x40, but it affected by
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temperature, so middle value change to 0x30 */
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#define PHY_DQ_MIDDLE_VAL 0x30303030
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#define PHY_MISC_SCRAMB_DIS 0xfffeffff /* scrambler disable */
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#define PHY_GATE_BDL_MAX 0xfe /* [6:0]rdqsg_bdl + [22:16]rdqsgtxbdl */
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#define PHY_DVRFTCTRL_PDAEN_EN 0x80000000 /* pda enable */
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/* [5] two cycle on address or command.(2T timing) */
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#define PHY_DRAMCFG_MA2T 0x20
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#define PHY_DRAMCFG_TYPE_DDR1 0x0 /* [2:0] 000 DDR1 */
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#define PHY_DRAMCFG_TYPE_DDR2 0x1 /* [2:0] 001 DDR2 */
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#define PHY_DRAMCFG_TYPE_DDR3 0x2 /* [2:0] 010 DDR3 */
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#define PHY_DRAMCFG_TYPE_DDR3L 0x3 /* [2:0] 011 DDR3L */
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#define PHY_DRAMCFG_TYPE_LPDDR1 0x4 /* [2:0] 100 LPDDR1 */
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#define PHY_DRAMCFG_TYPE_LPDDR2 0x5 /* [2:0] 101 LPDDR2 */
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#define PHY_DRAMCFG_TYPE_LPDDR3 0x5 /* [2:0] 101 LPDDR3 */
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#define PHY_DRAMCFG_TYPE_LPDDR4 0x6 /* [2:0] 110 LPDDR4 */
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#define PHY_DRAMCFG_TYPE_DDR4 0xa /* [3] 1010 DDR4 */
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#define PHY_DMSEL_SWAPDFIBYTE 0xf8ffffff /* [24:26] No Swap */
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/* other */
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#define PHY_RDQSG_PHASE_STEP 2 /* gate training phase step. */
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#define PHY_GATE_PHASE_MARGIN 8 /* gate phase margin */
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#define PHY_DQ_BDL_LEVEL 128 /* [CUSTOM] DQ BDL range */
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#define PHY_DQ_BDL_MIDDLE 64 /* special middle DQ BDL value */
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#define PHY_RDQSG_PHASE_MAX 0x3c /* RDQSG phase max value */
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#define PHY_ACPHY_CLK_MAX 0xf /* halft_dramclk0 + cp1p_dclk0 */
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#define PHY_PCODE_MIN 0x14
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#define PHY_PCODE_MAX 0x24
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/**
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* DDR_BDL_PHASE_REL Calculation Method:
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* 1. Calculation How many picosecond to one phase.
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* PICOSECOND : 1 second is (1000 * 1000 * 1000) picosecond
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* WAVE : 1 cycle is 2
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* RATE : DDR rate is 1600 Mbps, is (1600 * 1000) bps
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* PHASE : 1 wave is 12 phase
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* phase = (((PICOSECOND * WAVE) / RATE) / PHASE)
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* = (((1000 * 1000 * 1000 * 2) / (1600 * 1000)) / 12)
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* = 104.17 ps.
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* 2. Calculation How many bdl to one phase.
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* one BDL is 6 ps.
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* result = phase/bdl = 104.17 / 6 = 17.36 approximately equal to 17 ~= 16
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* 3. 16 = 1 << 4, so the relation is 4.
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*/
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#ifndef DDR_BDL_PHASE_TRANSFORM
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/* [CUSTOM] one Phase equal how much BDL. 1 phase = 16 bdl */
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#define DDR_BDL_PHASE_TRANSFORM 16
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#endif
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#ifndef DDR_BDL_PHASE_REL
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/* [CUSTOM] relation between BDL and Phase. 1 phase = 16 bdl, 16 = 1 << 4 */
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#define DDR_BDL_PHASE_REL 4
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#endif
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#define DDR_VARIABLE_DECLARE(var) \
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unsigned int var;
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#define DDR_VREF_GET_HOST_MAX(rank, val) \
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do { \
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if (0 == rank) \
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val = PHY_VRFTRES_HVREF_MASK; \
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else \
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val = PHY_VRFTRES_RXDIFFCAL_MASK; \
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} while (0)
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/* PHY t28 all byte use a same value */
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#define DDR_PHY_VREF_HOST_SET(base_phy, rank, bytenum, byte_index, val) \
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do { \
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unsigned int hvreft; \
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hvreft = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
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& (~PHY_VRFTRES_HVREF_MASK); \
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ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)); \
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ddr_write(hvreft | val, base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index + 1)); \
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} while (0)
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#define DDR_PHY_VREF_HOST_GET(base_phy, rank, byte_index, val) \
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do { \
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val = ddr_read(base_phy + DDR_PHY_HVREFT_STATUS(rank, byte_index)) \
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& PHY_VRFTRES_HVREF_MASK; \
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} while (0)
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#define DDR_PHY_VREF_HOST_DISPLAY \
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{0, 0, DDR_PHY_HVREFT_STATUS(0, 0), 0, "Host Vref Byte0"}, \
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{0, 1, DDR_PHY_HVREFT_STATUS(0, 1), 0, "Host Vref Byte1"}, \
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{0, 2, DDR_PHY_HVREFT_STATUS(0, 2), 0, "Host Vref Byte2"}, \
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{0, 3, DDR_PHY_HVREFT_STATUS(0, 3), 0, "Host Vref Byte3"},
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#define DDR_PHY_VREF_HOST_DISPLAY_RANK1 \
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{1, 0, DDR_PHY_HVREFT_STATUS(1, 0), 0, "Host Vref Byte0"}, \
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{1, 1, DDR_PHY_HVREFT_STATUS(1, 1), 0, "Host Vref Byte1"}, \
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{1, 2, DDR_PHY_HVREFT_STATUS(1, 2), 0, "Host Vref Byte2"}, \
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{1, 3, DDR_PHY_HVREFT_STATUS(1, 3), 0, "Host Vref Byte3"},
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#define DDR_PHY_VREF_HOST_DISPLAY_CMD(base_phy, rank, byte_num) \
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do { \
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unsigned int _i; \
|
|
for (_i = 0; _i < byte_num; _i++) { \
|
|
DDR_INFO("[%x = %x] Host Vref Byte(%x)", \
|
|
base_phy + DDR_PHY_HVREFT_STATUS(rank, _i), \
|
|
ddr_read(base_phy \
|
|
+ DDR_PHY_HVREFT_STATUS(rank, _i)), _i); \
|
|
} \
|
|
} while (0)
|
|
|
|
/* DRAM vref operations */
|
|
#define DDR_PHY_VREF_DRAM_SET(base_phy, val, byte_index) \
|
|
do { \
|
|
unsigned int dvrftctrl = \
|
|
ddr_read(base_phy + DDR_PHY_DVRFTCTRL); \
|
|
unsigned int dvreft = ddr_read(base_phy \
|
|
+ DDR_PHY_DVREFT_STATUS(byte_index)) \
|
|
& (~PHY_VRFTRES_DVREF_MASK); \
|
|
ddr_write(dvrftctrl | PHY_DVRFTCTRL_PDAEN_EN, \
|
|
base_phy + DDR_PHY_DVRFTCTRL); \
|
|
ddr_write(dvreft | val, \
|
|
base_phy + DDR_PHY_DVREFT_STATUS(byte_index)); \
|
|
ddr_write(PHY_PHYINITCTRL_DVREFT_SYNC \
|
|
| PHY_PHYINITCTRL_INIT_EN, \
|
|
base_phy + DDR_PHY_PHYINITCTRL); \
|
|
while (1) { \
|
|
if (!(ddr_read(base_phy + DDR_PHY_PHYINITCTRL) \
|
|
& PHY_PHYINITCTRL_INIT_EN)) \
|
|
break; \
|
|
} \
|
|
ddr_write(dvrftctrl & (~PHY_DVRFTCTRL_PDAEN_EN), \
|
|
base_phy + DDR_PHY_DVRFTCTRL); \
|
|
} while (0)
|
|
|
|
#define DDR_PHY_VREF_DRAM_GET(base_phy, val, byte_index) \
|
|
{ \
|
|
val = ddr_read(base_phy + DDR_PHY_DVREFT_STATUS(byte_index)) \
|
|
& PHY_VRFTRES_DVREF_MASK; \
|
|
}
|
|
|
|
#define DDR_PHY_VREF_DRAM_DISPLAY \
|
|
{0, 0, DDR_PHY_DVREFT_STATUS(0), 0, "DRAM Vref Byte0"}, \
|
|
{0, 1, DDR_PHY_DVREFT_STATUS(1), 0, "DRAM Vref Byte1"}, \
|
|
{0, 2, DDR_PHY_DVREFT_STATUS(2), 0, "DRAM Vref Byte2"}, \
|
|
{0, 3, DDR_PHY_DVREFT_STATUS(3), 0, "DRAM Vref Byte3"},
|
|
|
|
#define DDR_PHY_VREF_DRAM_DISPLAY_CMD(base_phy, byte_num) \
|
|
do { \
|
|
unsigned int _i; \
|
|
for (_i = 0; _i < byte_num; _i++) { \
|
|
DDR_INFO("[%x = %x] DRAM Vref Byte(%x)", \
|
|
base_phy + DDR_PHY_DVREFT_STATUS(_i), \
|
|
ddr_read(base_phy \
|
|
+ DDR_PHY_DVREFT_STATUS(_i)), _i); \
|
|
} \
|
|
} while (0)
|
|
|
|
/* phy t28 not support DCC training */
|
|
#define DDR_PHY_DCC_DISPLAY
|
|
#define DDR_PHY_DCC_DISPLAY_CMD(base_phy)
|
|
|
|
/* lowpower ddr ca operations */
|
|
#define DDR_PHY_ADDRPH_DISPLAY \
|
|
{0, 0, DDR_PHY_ADDRPHBOUND, 0, "CA Phase"},
|
|
|
|
#define DDR_PHY_ADDRBDL_DISPLAY \
|
|
{0, 0, DDR_PHY_ACADDRBDL(0), 0, "CA BDL(0)"}, \
|
|
{0, 0, DDR_PHY_ACADDRBDL(1), 0, "CA BDL(1)"}, \
|
|
{0, 0, DDR_PHY_ACADDRBDL(2), 0, "CA BDL(2)"}, \
|
|
{0, 0, DDR_PHY_ACADDRBDL(3), 0, "CA BDL(3)"}, \
|
|
{0, 0, DDR_PHY_ACADDRBDL(4), 0, "CA BDL(4)"},
|
|
|
|
#define DDR_PHY_ADDRPH_DISPLAY_CMD(base_phy) \
|
|
DDR_INFO("[%x = %x] CA Phase", \
|
|
base_phy + DDR_PHY_ADDRPHBOUND, \
|
|
ddr_read(base_phy + DDR_PHY_ADDRPHBOUND));
|
|
|
|
#define DDR_PHY_ADDRBDL_DISPLAY_CMD(base_phy) \
|
|
do { \
|
|
unsigned int _i; \
|
|
for (_i = 0; _i < DDR_PHY_CA_REG_MAX; _i++) { \
|
|
DDR_INFO("[%x = %x] ACADDRBDL(%x)", \
|
|
base_phy + DDR_PHY_ACADDRBDL(_i), \
|
|
ddr_read(base_phy \
|
|
+ DDR_PHY_ACADDRBDL(_i)), _i); \
|
|
} \
|
|
} while (0)
|
|
|
|
/* PHY t28 DDR4 RDQS synchronize to RDM */
|
|
#define DDR_PHY_RDQS_SYNC_RDM(cfg, val) \
|
|
ddr_rdqs_sync(cfg, val)
|
|
|
|
/* dqs swap */
|
|
#define DDR_DQSSWAP_SAVE_FUNC(swapdfibyte_en, base_phy) \
|
|
do { \
|
|
swapdfibyte_en = \
|
|
ddr_read(base_phy + DDR_PHY_DMSEL); \
|
|
ddr_write(swapdfibyte_en & PHY_DMSEL_SWAPDFIBYTE, \
|
|
base_phy + DDR_PHY_DMSEL); \
|
|
} while (0)
|
|
|
|
#define DDR_DQSSWAP_RESTORE_FUNC(swapdfibyte_en, base_phy) \
|
|
ddr_write(swapdfibyte_en, base_phy + DDR_PHY_DMSEL);
|
|
|
|
|
|
#define DDR_PHY_SWITCH_RANK(base_phy, val) \
|
|
do { \
|
|
ddr_write((ddr_read(base_phy + DDR_PHY_TRAINCTRL0) & (~PHY_TRAINCTRL0_MASK)) | val, base_phy + DDR_PHY_TRAINCTRL0); \
|
|
} while (0)
|
|
|
|
/* Define the union U_PHY_CATCONFIG */
|
|
union U_PHY_CATCONFIG {
|
|
/* Define the struct bits */
|
|
struct {
|
|
unsigned int ca_samp_num_bdl:4; /* [3:0] */
|
|
unsigned int ca_samp_num_ph:4; /* [7:4] */
|
|
unsigned int ca_trysamp_num:4; /* [11:8] */
|
|
unsigned int cat_rb_backtap:4; /* [15:12] */
|
|
unsigned int reserved:1; /* [16] */
|
|
unsigned int cat_openeye_en:1; /* [17] */
|
|
unsigned int cat_cat_phydq_sel:1; /* [18] */
|
|
unsigned int cat_restore_en:1; /* [19] */
|
|
unsigned int cat_lb_backtap:4; /* [23:20] */
|
|
unsigned int sw_cat_mrw42:1; /* [24] */
|
|
unsigned int sw_cat_mrw48:1; /* [25] */
|
|
unsigned int sw_cat_mrw41:1; /* [26] */
|
|
unsigned int sw_cat_strobe:1; /* [27] */
|
|
unsigned int sw_cat_cke_high:1; /* [28] */
|
|
unsigned int sw_cat_cke_low:1; /* [29] */
|
|
unsigned int sw_cat_dqvalid:1; /* [30] */
|
|
unsigned int sw_cat_en:1; /* [31] */
|
|
} bits;
|
|
|
|
/* Define an unsigned member */
|
|
unsigned int u32;
|
|
};
|
|
|
|
/* Define the union U_PHY_ADDRPHBOUND */
|
|
union U_PHY_ADDRPHBOUND {
|
|
/* Define the struct bits */
|
|
struct {
|
|
unsigned int addrph_a_right:5; /* [4:0] */
|
|
unsigned int reserved0:3; /* [7:5] */
|
|
unsigned int addrph_a_left:5; /* [12:8] */
|
|
unsigned int reserved1:3; /* [15:13] */
|
|
unsigned int addrph_a:5; /* [20:16] */
|
|
unsigned int reserved2:3; /* [23:21] */
|
|
unsigned int addrph_a_ori:5; /* [28:24] */
|
|
unsigned int reserved3:3; /* [31:29] */
|
|
} bits;
|
|
|
|
/* Define an unsigned member */
|
|
unsigned int u32;
|
|
};
|