133 lines
3.6 KiB
C
Executable File
133 lines
3.6 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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#ifndef DDR_TRAINING_INTERNAL_CONFIG_H
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#define DDR_TRAINING_INTERNAL_CONFIG_H
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/****** include ddrc,phy,dmc define files *******************/
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#include "ddr_ddrc.h"
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#include "ddr_phy.h"
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#include "ddr_ddrt_v2_0_shf1.h"
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/****** training item define *******************/
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/* enable all config by default */
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#define DDR_WL_TRAINING_CONFIG
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#define DDR_GATE_TRAINING_CONFIG
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#define DDR_DATAEYE_TRAINING_CONFIG
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#define DDR_HW_TRAINING_CONFIG
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#define DDR_TRAINING_ADJUST_CONFIG
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#define DDR_TRAINING_LOG_CONFIG
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#define DDR_TRAINING_UART_CONFIG
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#define DDR_TRAINING_STAT_CONFIG
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/* defined in ddr_training_custom.h to disable this item */
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#ifdef DDR_VREF_TRAINING_DISABLE
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#undef DDR_VREF_TRAINING_CONFIG
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#endif
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#ifdef DDR_WL_TRAINING_DISABLE
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#undef DDR_WL_TRAINING_CONFIG
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#endif
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#ifdef DDR_GATE_TRAINING_DISABLE
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#undef DDR_GATE_TRAINING_CONFIG
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#endif
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#ifdef DDR_DATAEYE_TRAINING_DISABLE
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#undef DDR_DATAEYE_TRAINING_CONFIG
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#endif
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#ifdef DDR_HW_TRAINING_DISABLE
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#undef DDR_HW_TRAINING_CONFIG
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#endif
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#ifdef DDR_MPR_TRAINING_DISABLE
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#undef DDR_MPR_TRAINING_CONFIG
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#endif
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#ifdef DDR_TRAINING_ADJUST_DISABLE
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#undef DDR_TRAINING_ADJUST_CONFIG
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#endif
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#ifdef DDR_TRAINING_LOG_DISABLE
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#undef DDR_TRAINING_LOG_CONFIG
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#endif
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#ifdef DDR_TRAINING_UART_DISABLE
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#undef DDR_TRAINING_UART_CONFIG
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#endif
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#ifdef DDR_TRAINING_STAT_DISABLE
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#undef DDR_TRAINING_STAT_CONFIG
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#endif
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/* for training cmd */
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#ifdef DDR_TRAINING_CMD
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/* defined in ddr_training_custom.h to disable this item */
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#ifdef DDR_VREF_TRAINING_CMD_DISABLE
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#undef DDR_VREF_TRAINING_CONFIG
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#endif
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#ifdef DDR_WL_TRAINING_CMD_DISABLE
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#undef DDR_WL_TRAINING_CONFIG
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#endif
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#ifdef DDR_GATE_TRAINING_CMD_DISABLE
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#undef DDR_GATE_TRAINING_CONFIG
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#endif
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#ifdef DDR_DATAEYE_TRAINING_CMD_DISABLE
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#undef DDR_DATAEYE_TRAINING_CONFIG
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#endif
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#ifdef DDR_HW_TRAINING_CMD_DISABLE
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#undef DDR_HW_TRAINING_CONFIG
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#endif
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#ifdef DDR_MPR_TRAINING_CMD_DISABLE
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#undef DDR_MPR_TRAINING_CONFIG
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#endif
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#ifdef DDR_TRAINING_ADJUST_CMD_DISABLE
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#undef DDR_TRAINING_ADJUST_CONFIG
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#endif
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#ifdef DDR_TRAINING_LOG_CMD_DISABLE
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#undef DDR_TRAINING_LOG_CONFIG
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#endif
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#endif /* DDR_TRAINING_CMD */
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/* check config */
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#if defined(DDR_TRAINING_ADJUST_DISABLE) && defined(DDR_HW_TRAINING_CONFIG) \
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&& !defined(DDR_HW_READ_ADJ_CONFIG)
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#error when defined DDR_TRAINING_ADJUST_DISABLE, \
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MUST define DDR_HW_READ_ADJ_CONFIG.
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#endif
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#if (defined(DDR_HW_TRAINING_CONFIG) || defined(DDR_MPR_TRAINING_CONFIG) \
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|| defined(DDR_VREF_TRAINING_CONFIG) \
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|| defined(DDR_TRAINING_ADJUST_CONFIG)) \
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&& !defined(DDR_DATAEYE_TRAINING_CONFIG)
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#error when enable HW/GATE/VREF training or dataeye adjust, \
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MUST define DDR_DATAEYE_TRAINING_CONFIG.
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#endif
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/* reserve config */
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/* DDR_WL_DATAEYE_ADJUST_CONFIG: Adjust WDQ phase/bdl after WL training. */
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/* DDR_VREF_TRAINING_CONFIG : DDR Vref training. */
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/* DDR_MPR_TRAINING_CONFIG : DDR MPR training. */
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/* DDR_AC_TRAINING_CONFIG : DDR AC training. */
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/* DDR_LPCA_TRAINING_CONFIG : LPDDR CA training. */
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/* DDR_DDRT_SPECIAL_CONFIG : DDRT read and write special operate. */
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/* DDR_DDR4_CONFIG : DDR4 special operate. */
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/* DDR_TRAINING_CUT_CODE_CONFIG: Cut code for small SRAM. */
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/* DDR_TRAINING_MINI_LOG_CONFIG: Less code to log */
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/* DDR_HW_READ_ADJ_CONFIG : Adjust read dataeye after hw read training */
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/* DDR_VREF_WITHOUT_BDL_CONFIG : Vref not modify DQ bdl */
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/* DDR_DATAEYE_NORMAL_NOT_ADJ_CONFIG : Do not adjust window on normal case */
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#endif /* DDR_TRAINING_INTERNAL_CONFIG_H */
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