164 lines
4.7 KiB
C
Executable File
164 lines
4.7 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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/*****************************************************************************/
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#define GD_SPI_CMD_RDSR1 0x35 /* Read Status Register-1 */
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/*****************************************************************************/
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/*
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* enable QE bit if QUAD read write is supported by GD "25qxxx" SPI
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*/
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static void set_cmd(struct fmc_spi *spi, u8 cmd, u8 len)
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{
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struct fmc_host *host = (struct fmc_host *)spi->host;
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unsigned int regval;
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regval = fmc_cmd_cmd1(cmd);
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fmc_write(host, FMC_CMD, regval);
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fmc_pr(QE_DBG, "\t|-Set CMD[%#x]%#x\n", FMC_CMD, regval);
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regval = op_cfg_fm_cs(spi->chipselect) | OP_CFG_OEN_EN;
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fmc_write(host, FMC_OP_CFG, regval);
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fmc_pr(QE_DBG, "\t|-Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, regval);
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regval = fmc_data_num_cnt(len);
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fmc_write(host, FMC_DATA_NUM, regval);
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fmc_pr(QE_DBG, "\t|-Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, regval);
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regval = fmc_op_cmd1_en(ENABLE) |
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fmc_op_write_data_en(ENABLE) |
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FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, regval);
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fmc_pr(QE_DBG, "\t|-Set OP[%#x]%#x\n", FMC_OP, regval);
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fmc_cmd_wait_cpu_finish(host);
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spi->driver->wait_ready(spi);
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}
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static int gd_16pin_qe_enable(struct fmc_spi *spi, int op)
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{
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struct fmc_host *host = (struct fmc_host *)spi->host;
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unsigned char config;
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unsigned char status;
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const char *str[] = {"Disable", "Enable"};
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config = spi_general_get_flash_register(spi, GD_SPI_CMD_RDSR1);
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fmc_pr(QE_DBG, "\t|-Read GD SR-1[%#x], val: %#x\n", GD_SPI_CMD_RDSR1,
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config);
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if (op && (op == spi_nor_get_qe_by_cr(config))) {
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fmc_pr(QE_DBG, "\t* Quad was %sd, status:%#x\n", str[op],
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config);
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return op;
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}
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/* First, we enable/disable QE for 16Pin GD flash, use WRSR[01h] cmd */
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fmc_pr(QE_DBG, "\t|-First, 16Pin GD flash %s Quad.\n", str[op]);
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status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
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fmc_pr(QE_DBG, "\t|-Read Status Register[%#x]%#x\n", SPI_CMD_RDSR,
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status);
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spi->driver->write_enable(spi);
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if (op)
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config |= SPI_NOR_CR_QE_MASK;
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else
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config &= ~SPI_NOR_CR_QE_MASK;
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writeb(status, host->iobase);
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writeb(config, host->iobase + SPI_NOR_SR_LEN);
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fmc_pr(QE_DBG, "\t|-Write IO[%p]%#x\n", host->iobase,
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*(unsigned short *)host->iobase);
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set_cmd(spi, SPI_CMD_WRSR, SPI_NOR_SR_LEN + SPI_NOR_CR_LEN);
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config = spi_general_get_flash_register(spi, GD_SPI_CMD_RDSR1);
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fmc_pr(QE_DBG, "\t|-Read GD SR-1[%#x], val: %#x\n", GD_SPI_CMD_RDSR1,
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config);
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if (op == spi_nor_get_qe_by_cr(config)) {
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fmc_pr(QE_DBG, "\t|-16P %s Quad success reg: %#x\n", str[op],
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config);
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return op;
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} else {
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fmc_pr(QE_DBG, "\t|-16P %s Quad failed, reg: %#x\n", str[op],
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config);
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}
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return 0;
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}
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static void gd_8pin_qe_enable(struct fmc_spi *spi, int op)
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{
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unsigned char config;
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unsigned char status;
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const char *str[] = {"Disable", "Enable"};
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struct fmc_host *host = (struct fmc_host *)spi->host;
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fmc_pr(QE_DBG, "\t|-Second, 8Pin GD flash %s Quad.\n", str[op]);
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status = spi_general_get_flash_register(spi, SPI_CMD_RDSR);
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fmc_pr(QE_DBG, "\t|-Read Status Register[%#x]:%#x\n", SPI_CMD_RDSR,
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status);
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if (!(status & STATUS_WEL_MASK))
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spi->driver->write_enable(spi);
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config = spi_general_get_flash_register(spi, SPI_CMD_RDSR2);
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fmc_pr(QE_DBG, "\t|-Read SR-2[%#x], val: %#x\n", SPI_CMD_RDSR2,
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config);
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if (op && (op == spi_nor_get_qe_by_cr(config))) {
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fmc_pr(QE_DBG, "\t* Quad was %sd, status:%#x\n", str[op],
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config);
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return;
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}
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if (op)
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config |= SPI_NOR_CR_QE_MASK;
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else
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config &= ~SPI_NOR_CR_QE_MASK;
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writeb(config, host->iobase);
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fmc_pr(QE_DBG, "\t|-Write IO[%p]%#x\n", host->iobase,
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*(unsigned char *)host->iobase);
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set_cmd(spi, SPI_CMD_WRSR2, SPI_NOR_CR_LEN);
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config = spi_general_get_flash_register(spi, SPI_CMD_RDSR2);
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fmc_pr(QE_DBG, "\t|-Read GD SR-2[%#x], val: %#x\n", SPI_CMD_RDSR2,
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config);
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if (op == spi_nor_get_qe_by_cr(config))
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fmc_pr(QE_DBG, "\t|-8P %s Quad success, reg: %#x.\n", str[op],
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config);
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else
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db_msg("Error: %s Quad failed, reg: %#x\n", str[op], config);
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return;
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}
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static int spi_gd25qxxx_qe_enable(struct fmc_spi *spi)
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{
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unsigned char op;
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const char *str[] = {"Disable", "Enable"};
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op = spi_is_quad(spi);
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fmc_pr(QE_DBG, "\t*-Start GD SPI nor %s Quad.\n", str[op]);
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/* First, we enable/disable QE for 16Pin GD flash, use WRSR[01h] cmd */
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if (gd_16pin_qe_enable(spi, op))
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goto QE_END;
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/* Second, we enable/disable QE for 8Pin GD flash, use WRSR2[31h] cmd */
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gd_8pin_qe_enable(spi, op);
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QE_END:
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/* Enable the reset pin when working on dual mode for 8PIN */
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if (!op)
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spi_nor_reset_pin_enable(spi, ENABLE);
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fmc_pr(QE_DBG, "\t*-End GD SPI nor %s Quad end.\n", str[op]);
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return op;
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}
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