81 lines
2.4 KiB
C
Executable File
81 lines
2.4 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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/*****************************************************************************/
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static int spi_puya_entry_4addr(struct fmc_spi *spi, int enable)
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{
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return 0;
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}
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/****************************************************************************/
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/*
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* enable QE bit if QUAD read write is supported by puya'a P25Q128H,it is as same as W25Q(128/256)FV
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* opcode type name
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* 0x35 RD SR(S15-S8)
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* 0x31 WR SR(S15-S8)
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*/
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static int spi_puya_qe_enable(struct fmc_spi *spi)
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{
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unsigned char status;
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unsigned char op;
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unsigned int regval;
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const char *str[] = {"Disable", "Enable"};
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struct fmc_host *host = (struct fmc_host *)spi->host;
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op = spi_is_quad(spi);
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fmc_pr(QE_DBG, "\t* Start SPI Nor %s Quad.\n", str[op]);
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status = spi_general_get_flash_register(spi, SPI_CMD_RDSR2);
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fmc_pr(QE_DBG, "\t Read Status Register-2[%#x]%#x\n", SPI_CMD_RDSR2,
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status);
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if (spi_nor_get_qe_by_cr(status) == op) {
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fmc_pr(QE_DBG, "\t* Quad was %s status:%#x\n", str[op], status);
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goto QE_END;
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}
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spi->driver->write_enable(spi);
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if (op)
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status |= SPI_NOR_CR_QE_MASK;
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else
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status &= ~SPI_NOR_CR_QE_MASK;
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writeb(status, host->iobase);
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fmc_pr(QE_DBG, "\t Write IO[%#lx]%#x\n", (uintptr_t)host->iobase,
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*(unsigned char *)host->iobase);
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/* There is new cmd for Write Status Register 2 by W25Q(128/256)FV */
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regval = fmc_cmd_cmd1(SPI_CMD_WRSR2);
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fmc_write(host, FMC_CMD, regval);
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fmc_pr(QE_DBG, "\t Set CMD[%#x]%#x\n", FMC_CMD, regval);
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regval = op_cfg_fm_cs(spi->chipselect);
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fmc_write(host, FMC_OP_CFG, regval);
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fmc_pr(QE_DBG, "\t Set OP_CFG[%#x]%#x\n", FMC_OP_CFG, regval);
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regval = fmc_data_num_cnt(SPI_NOR_SR_LEN);
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fmc_write(host, FMC_DATA_NUM, regval);
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fmc_pr(QE_DBG, "\t Set DATA_NUM[%#x]%#x\n", FMC_DATA_NUM, regval);
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regval = fmc_op_cmd1_en(ENABLE) |
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fmc_op_write_data_en(ENABLE) | FMC_OP_REG_OP_START;
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fmc_write(host, FMC_OP, regval);
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fmc_pr(QE_DBG, "\t Set OP[%#x]%#x\n", FMC_OP, regval);
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fmc_cmd_wait_cpu_finish(host);
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/* wait the flash have switched quad mode success */
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spi->driver->wait_ready(spi);
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status = spi_general_get_flash_register(spi, SPI_CMD_RDSR2);
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fmc_pr(QE_DBG, "\t Read Status Register-2[%#x]:%#x\n",
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SPI_CMD_RDSR2, status);
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if (spi_nor_get_qe_by_cr(status) == op)
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fmc_pr(QE_DBG, "\t %s Quad success. status:%#x\n",
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str[op], status);
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else
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db_msg("Error: %s Quad failed! reg:%#x\n", str[op], status);
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QE_END:
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return op;
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} |