520 lines
13 KiB
ArmAsm
Executable File
520 lines
13 KiB
ArmAsm
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/system.h>
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#include <linux/linkage.h>
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#include <asm/armv7.h>
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/*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* Do important init only if we don't start from memory!
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* Setup memory and board specific bits prior to relocation.
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* Relocate armboot to ram. Setup stack.
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*
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*************************************************************************/
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.globl _start
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_start:
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b reset
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b .
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b .
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b .
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b .
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b .
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b .
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b .
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.balignl 64,0xdeadbeef
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.globl reset
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.globl save_boot_params_ret
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#ifdef CONFIG_ARMV7_LPAE
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.global switch_to_hypervisor_ret
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#endif
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__blank_zone_start:
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.fill 1024*5,1,0
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__blank_zone_end:
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.globl _blank_zone_start
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_blank_zone_start:
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.word __blank_zone_start
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.globl _blank_zone_end
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_blank_zone_end:
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.word __blank_zone_end
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.balignl 16,0xdeadbeef
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.globl _TEXT_BASE
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_TEXT_BASE:
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.word TEXT_BASE
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_clr_remap_fmc_entry:
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.word FMC_MEM_BASE + do_clr_remap - CONFIG_SYS_TEXT_BASE_ORI
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_start_armboot:
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.word start_armboot
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reset:
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/* Allow the board to save important registers */
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b save_boot_params
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save_boot_params_ret:
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#ifdef CONFIG_ARMV7_LPAE
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/*
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* check for Hypervisor support
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*/
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mrc p15, 0, r0, c0, c1, 1 @ read ID_PFR1
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and r0, r0, #CPUID_ARM_VIRT_MASK @ mask virtualization bits
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cmp r0, #(1 << CPUID_ARM_VIRT_SHIFT)
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beq switch_to_hypervisor
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switch_to_hypervisor_ret:
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#endif
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/*
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* disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
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* except if in HYP mode already
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*/
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mrs r0, cpsr
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and r1, r0, #0x1f @ mask mode bits
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teq r1, #0x1a @ test for HYP mode
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bicne r0, r0, #0x1f @ clear all mode bits
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orrne r0, r0, #0x13 @ set SVC mode
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orr r0, r0, #0xc0 @ disable FIQ and IRQ
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msr cpsr,r0
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/*
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* Setup vector:
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* (OMAP4 spl TEXT_BASE is not 32 byte aligned.
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* Continue to use ROM code vector only in OMAP4 spl)
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*/
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#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD))
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/* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */
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mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register
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bic r0, #CR_V @ V = 0
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mcr p15, 0, r0, c1, c0, 0 @ Write CP15 SCTLR Register
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/* Set vector address in CP15 VBAR register */
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adrl r0, _start
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mcr p15, 0, r0, c12, c0, 0 @Set VBAR
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#endif
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/* the mask ROM code should have PLL and others stable */
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_cp15
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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bl cpu_init_crit
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#endif
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#endif
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#ifndef CONFIG_GK_DISABLE_DOWNLOAD
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/*
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* read system register REG_SC_GEN2
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* check if ziju flag
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*/
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ldr r0, =SYS_CTRL_REG_BASE
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ldr r1, [r0, #REG_SC_GEN2]
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ldr r2, =0x7a696a75 /* magic for "ziju" */
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cmp r1, r2
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bne normal_start_flow
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mov r1, sp /* save sp */
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str r1, [r0, #REG_SC_GEN2] /* clear ziju flag */
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/* init PLL/DDRC/pin mux/... */
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ldr r0, _blank_zone_start
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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ldr r1, =RAM_START_ADRS
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ldr sp, =STACK_TRAINING
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add r0, r0, r1
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mov r1, #0x0 /* flags: 0->normal 1->pm */
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bl init_registers /* init PLL/DDRC/... */
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/* after ziju, we need ddr traning */
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ldr r0, =SYS_CTRL_REG_BASE
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bl start_ddr_training /* DDR training */
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ldr r0, =SYS_CTRL_REG_BASE
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ldr r1, [r0, #REG_SC_GEN2]
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mov sp, r1 /* restore sp */
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ldr r1, [r0, #REG_SC_GEN3]
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mov pc, r1 /* return to bootrom */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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b . /* bug here */
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normal_start_flow:
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#endif
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/* init serial and printf a string. */
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ldr sp, =STACK_TRAINING
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#ifdef ENABLE_MINI_BOOT
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bl timer_init
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#else
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bl uart_early_init
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bl msg_main_cpu_startup
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#endif
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/*
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* enable syscnt
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*/
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ldr r0, =SYSCNT_REG_BASE
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ldr r3, =SYSCNT_FREQ
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str r3, [r0, #SYSCNT_FREQ_REG]
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mov r3, #0x1
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str r3, [r0, #SYSCNT_ENABLE_REG]
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@if running not boot from nand/spi/emmc,
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@we skipping boot_type checking.
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mov r0, pc, lsr#24
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cmp r0, #0x0
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bne do_clr_remap
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check_boot_type:
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#ifndef ENABLE_MINI_BOOT
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ldr r0, =SYS_CTRL_REG_BASE
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ldr r0, [r0, #REG_SYSSTAT]
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mov r6, r0, lsr#4
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and r6, #0x1
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cmp r6, #0x1
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ldrlo pc, _clr_remap_fmc_entry
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#else
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ldr pc, _clr_remap_fmc_entry
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#endif
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do_clr_remap:
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#ifndef ENABLE_MINI_BOOT
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/* do clear remap */
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ldr r4, =SYS_CTRL_REG_BASE
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ldr r0, [r4, #REG_SC_CTRL]
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@Set clear remap bit.
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orr r0, #(1<<8)
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str r0, [r4, #REG_SC_CTRL]
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#endif
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@enable I-Cache now
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mrc p15, 0, r0, c1, c0, 0
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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mcr p15, 0, r0, c1, c0, 0
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@Check wether I'm running in dynamic mem bank:<0x40000000
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mov r0, pc, lsr#28
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cmp r0, #4
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blo ddr_init
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no_ddr_init:
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adrl r0, _start
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b copy_to_ddr
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ddr_init:
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ldr r0, _blank_zone_start
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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adrl r1, _start
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add r0, r0, r1
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mov r1, #0 /* flags: 0->normal 1->pm */
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bl init_registers
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ldr sp, =STACK_TRAINING
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ldr r0, =SYS_CTRL_REG_BASE
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bl start_ddr_training /* DDR training */
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check_boot_mode:
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#ifndef ENABLE_MINI_BOOT
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ldr r0, =SYS_CTRL_REG_BASE
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ldr r0, [r0, #REG_SYSSTAT]
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mov r6, r0, lsr#4
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and r6, #0x1
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cmp r6, #BOOT_FROM_EMMC
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bne copy_flash_to_ddr
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#else
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b copy_flash_to_ddr
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#endif
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#ifndef ENABLE_MINI_BOOT
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emmc_boot:
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ldr r0, _TEXT_BASE
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ldr r1, =__image_copy_start
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ldr r2, =__bss_start
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sub r1, r2, r1
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bl emmc_boot_read
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b relocate
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#endif
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copy_flash_to_ddr:
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/* relocate SPI nor/nand Boot to DDR */
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ldr r0, =FMC_MEM_BASE
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copy_to_ddr:
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/* now, r0 stores __reset offset from where we get started */
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ldr r1, =__image_copy_start
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/* compare source and target address, *
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*if equal no copy to target address */
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cmp r0, r1
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beq start_armboot
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ldr r2, =__image_copy_start/*_start*/
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ldr r3, =__bss_start
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sub r2, r3, r2 /* r2 <- size of armboot */
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/* memcpy(r1, r0, r2) */
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bl memcpy
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relocate:
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ldr r0, =_start_armboot
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ldr pc, [r0]
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bug:
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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b . /* bug here */
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@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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@
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@ void memcpy(r1, r0, r2);
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@
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.align 2
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memcpy:
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add r2, r0, r2
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memcpy_loop:
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ldmia r0!, {r3 - r10}
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stmia r1!, {r3 - r10}
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cmp r0, r2
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ble memcpy_loop
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mov pc, lr
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@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
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.align 2
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msg_main_cpu_startup:
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mov r5, lr
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add r0, pc, #4
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bl uart_early_puts
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mov pc, r5
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L10:
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#ifndef CONFIG_SUPPORT_CA_RELEASE
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.ascii "\r\n\r\nSystem startup\r\n\0"
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#else
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.ascii "\r\n\r\n\r\n\0"
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#endif
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/*------------------------------------------------------------------------------*/
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ENTRY(c_runtime_cpu_setup)
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/*
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* If I-cache is enabled invalidate it
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*/
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#ifndef CONFIG_SYS_ICACHE_OFF
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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#endif
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bx lr
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ENDPROC(c_runtime_cpu_setup)
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/*************************************************************************
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*
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* void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
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* __attribute__((weak));
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*
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* Stack pointer is not yet initialized at this moment
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* Don't save anything to stack even if compiled with -O0
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*
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*************************************************************************/
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ENTRY(save_boot_params)
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b save_boot_params_ret @ back to my caller
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ENDPROC(save_boot_params)
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.weak save_boot_params
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#ifdef CONFIG_ARMV7_LPAE
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ENTRY(switch_to_hypervisor)
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b switch_to_hypervisor_ret
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ENDPROC(switch_to_hypervisor)
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.weak switch_to_hypervisor
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#endif
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/*************************************************************************
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*
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* cpu_init_cp15
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*
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* Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
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* CONFIG_SYS_ICACHE_OFF is defined.
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*
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*************************************************************************/
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ENTRY(cpu_init_cp15)
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/*
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* Invalidate L1 I/D
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*/
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mov r0, #0 @ set up for MCR
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mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
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mcr p15, 0, r0, c7, c5, 6 @ invalidate BP array
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mcr p15, 0, r0, c7, c10, 4 @ DSB
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mcr p15, 0, r0, c7, c5, 4 @ ISB
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/*
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* disable MMU stuff and caches
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
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bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
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orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
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orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
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#ifdef CONFIG_SYS_ICACHE_OFF
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bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
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#else
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orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
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#endif
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mcr p15, 0, r0, c1, c0, 0
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#ifdef CONFIG_ARM_ERRATA_716044
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mrc p15, 0, r0, c1, c0, 0 @ read system control register
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orr r0, r0, #1 << 11 @ set bit #11
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mcr p15, 0, r0, c1, c0, 0 @ write system control register
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#endif
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#if (defined(CONFIG_ARM_ERRATA_742230) || defined(CONFIG_ARM_ERRATA_794072))
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 4 @ set bit #4
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_743622
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 6 @ set bit #6
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_751472
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 11 @ set bit #11
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_761320
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mrc p15, 0, r0, c15, c0, 1 @ read diagnostic register
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orr r0, r0, #1 << 21 @ set bit #21
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mcr p15, 0, r0, c15, c0, 1 @ write diagnostic register
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#endif
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mov r5, lr @ Store my Caller
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mrc p15, 0, r1, c0, c0, 0 @ r1 has Read Main ID Register (MIDR)
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mov r3, r1, lsr #20 @ get variant field
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and r3, r3, #0xf @ r3 has CPU variant
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and r4, r1, #0xf @ r4 has CPU revision
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mov r2, r3, lsl #4 @ shift variant field for combined value
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orr r2, r4, r2 @ r2 has combined CPU variant + revision
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#ifdef CONFIG_ARM_ERRATA_798870
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cmp r2, #0x30 @ Applies to lower than R3p0
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bge skip_errata_798870 @ skip if not affected rev
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cmp r2, #0x20 @ Applies to including and above R2p0
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blt skip_errata_798870 @ skip if not affected rev
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mrc p15, 1, r0, c15, c0, 0 @ read l2 aux ctrl reg
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orr r0, r0, #1 << 7 @ Enable hazard-detect timeout
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_l2aux_ctrl
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isb @ Recommended ISB after l2actlr update
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pop {r1-r5} @ Restore the cpu info - fall through
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skip_errata_798870:
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#endif
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#ifdef CONFIG_ARM_ERRATA_801819
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cmp r2, #0x24 @ Applies to lt including R2p4
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bgt skip_errata_801819 @ skip if not affected rev
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cmp r2, #0x20 @ Applies to including and above R2p0
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blt skip_errata_801819 @ skip if not affected rev
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mrc p15, 0, r0, c0, c0, 6 @ pick up REVIDR reg
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and r0, r0, #1 << 3 @ check REVIDR[3]
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cmp r0, #1 << 3
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beq skip_errata_801819 @ skip erratum if REVIDR[3] is set
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mrc p15, 0, r0, c1, c0, 1 @ read auxilary control register
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orr r0, r0, #3 << 27 @ Disables streaming. All write-allocate
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@ lines allocate in the L1 or L2 cache.
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orr r0, r0, #3 << 25 @ Disables streaming. All write-allocate
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@ lines allocate in the L1 cache.
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_acr
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pop {r1-r5} @ Restore the cpu info - fall through
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skip_errata_801819:
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#endif
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#ifdef CONFIG_ARM_ERRATA_454179
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cmp r2, #0x21 @ Only on < r2p1
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bge skip_errata_454179
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mrc p15, 0, r0, c1, c0, 1 @ Read ACR
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orr r0, r0, #(0x3 << 6) @ Set DBSM(BIT7) and IBE(BIT6) bits
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_acr
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pop {r1-r5} @ Restore the cpu info - fall through
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skip_errata_454179:
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#endif
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#ifdef CONFIG_ARM_ERRATA_430973
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cmp r2, #0x21 @ Only on < r2p1
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bge skip_errata_430973
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mrc p15, 0, r0, c1, c0, 1 @ Read ACR
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orr r0, r0, #(0x1 << 6) @ Set IBE bit
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push {r1-r5} @ Save the cpu info registers
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bl v7_arch_cp15_set_acr
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pop {r1-r5} @ Restore the cpu info - fall through
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skip_errata_430973:
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#endif
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#ifdef CONFIG_ARM_ERRATA_621766
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cmp r2, #0x21 @ Only on < r2p1
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bge skip_errata_621766
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mrc p15, 0, r0, c1, c0, 1 @ Read ACR
|
|
orr r0, r0, #(0x1 << 5) @ Set L1NEON bit
|
|
push {r1-r5} @ Save the cpu info registers
|
|
bl v7_arch_cp15_set_acr
|
|
pop {r1-r5} @ Restore the cpu info - fall through
|
|
|
|
skip_errata_621766:
|
|
#endif
|
|
|
|
mov pc, r5 @ back to my caller
|
|
ENDPROC(cpu_init_cp15)
|
|
|
|
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
|
|
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
|
|
/*************************************************************************
|
|
*
|
|
* CPU_init_critical registers
|
|
*
|
|
* setup important registers
|
|
* setup memory timing
|
|
*
|
|
*************************************************************************/
|
|
ENTRY(cpu_init_crit)
|
|
/*
|
|
* Jump to board specific initialization...
|
|
* The Mask ROM will have already initialized
|
|
* basic memory. Go here to bump up clock rate and handle
|
|
* wake up conditions.
|
|
*/
|
|
b lowlevel_init @ go setup pll,mux,memory
|
|
ENDPROC(cpu_init_crit)
|
|
#endif
|
|
|