104 lines
3.1 KiB
C
Executable File
104 lines
3.1 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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#ifndef DDR_TRAINING_CUSTOM_H
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#define DDR_TRAINING_CUSTOM_H
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/* config DDRC, PHY, DDRT typte */
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#define DDR_DDRC_V520_CONFIG
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#define DDR_PHY_T28_CONFIG
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#define DDR_DDRT_V2_0_SHF1_CONFIG
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/* config special item */
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#define DDR_VREF_TRAINING_CONFIG
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#define DDR_VREF_WITHOUT_BDL_CONFIG
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//#define DDR_PCODE_TRAINING_CONFIG
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#define DDR_WL_TRAINING_DISABLE
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#define DDR_GATE_TRAINING_DISABLE
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#define DDR_TRAINING_UART_DISABLE
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/* Disable write dm
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#define DDR_WRITE_DM_DISABLE */
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#define DDR_PHY_NUM 1 /* phy number */
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#define DDR_DMC_PER_PHY_MAX 2 /* dmc number per phy max */
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#define DDR_AXI_SWITCH_NUM 4 /* ddr training axi switch number */
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/* config DDRC, PHY, DDRT base address */
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/* [CUSTOM] DDR PHY0 base register */
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#define DDR_REG_BASE_PHY0 0x120dc000
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/* [CUSTOM] DDR PHY1 base register
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#define DDR_REG_BASE_PHY1 0x120de000 */
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/* [CUSTOM] DDR DMC0 base register */
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#define DDR_REG_BASE_DMC0 0x120d8000
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/* [CUSTOM] DDR DMC1 base register */
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#define DDR_REG_BASE_DMC1 0x120d8000
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#ifdef DDR_REG_BASE_PHY1
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/* [CUSTOM] DDR DMC2 base register */
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#define DDR_REG_BASE_DMC2 0x120d9000
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/* [CUSTOM] DDR DMC3 base register */
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#define DDR_REG_BASE_DMC3 0x120d9000
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#endif
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/* [CUSTOM] DDR DDRT base register */
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#define DDR_REG_BASE_DDRT 0x11330000
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/* [CUSTOM] DDR training item system control */
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#define DDR_REG_BASE_SYSCTRL 0x12020000
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#define DDR_REG_BASE_AXI 0x120d0000
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/* Serial Configuration */
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#define DDR_REG_BASE_UART0 0x12040000
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/* config offset address */
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/* Assume sysctrl offset address for DDR training as follows,
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if not please define. */
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/* [CUSTOM] ddrt reversed data */
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#define SYSCTRL_DDRT_PATTERN 0xa8
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/* [CUSTOM] PHY2 ddrt reversed data
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#define SYSCTRL_DDRT_PATTERN_SEC 0xac */
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/* [CUSTOM] ddr training item */
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#define SYSCTRL_DDR_TRAINING_CFG 0xa0
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#define SYSCTRL_DDR_TRAINING_CFG_SEC 0xa4
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/* [CUSTOM] ddr training version flag */
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#define SYSCTRL_DDR_TRAINING_VERSION_FLAG 0xb4
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/* [CUSTOM] ddr training stat */
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#define SYSCTRL_DDR_TRAINING_STAT 0xb0
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/* [CUSTOM] ddr hw training item */
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#define SYSCTRL_DDR_HW_PHY0_RANK0 0x90
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#define SYSCTRL_DDR_HW_PHY0_RANK1 0x94
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#if 0
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/* PHY1 hw training item */
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#define SYSCTRL_DDR_HW_PHY1_RANK0 0x98
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#define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c
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#endif
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/* config other special */
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/* [CUSTOM] DDR training start address. MEM_BASE_DDR */
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#define DDRT_CFG_BASE_ADDR 0x40000000
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/* [CUSTOM] SRAM start address.
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NOTE: Makefile will parse it, plase define it as Hex. eg: 0xFFFF0C00 */
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#define DDR_TRAINING_RUN_STACK 0x04010c00
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#define DDR_RELATE_REG_DECLARE
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#define DDR_TRAINING_SAVE_REG_FUNC(relate_reg, mask) \
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ddr_training_save_reg_custom(relate_reg, mask)
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#define DDR_TRAINING_RESTORE_REG_FUNC(relate_reg) \
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ddr_training_restore_reg_custom(relate_reg)
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struct tr_custom_reg {
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unsigned int ive_ddrt_mst_sel;
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unsigned int ddrt_clk_reg;
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unsigned int phy0_age_compst_en;
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unsigned int phy1_age_compst_en;
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};
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void ddr_training_save_reg_custom(void *relate_reg, unsigned int mask);
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void ddr_training_restore_reg_custom(void *relate_reg);
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int ddr_get_cksel(void);
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#endif /* DDR_TRAINING_CUSTOM_H */
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