106 lines
2.9 KiB
C
Executable File
106 lines
2.9 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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#include "ddr_interface.h"
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#include "ddr_training_impl.h"
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#define CRG_REG_BASE 0x12010000U
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#define PERI_CRG_DDRT 0x198U
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#define PERI_CRG_DDRCKSEL 0x80U
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/* [SYSCTRL]RAM Retention control register 0 */
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#define SYSCTRL_MISC_CTRL4 0x8010U
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static struct tr_relate_reg relate_reg;
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static struct tr_relate_reg *reg = &relate_reg;
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/**
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* Do some prepare before copy code from DDR to SRAM.
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* Keep empty when nothing to do.
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*/
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void ddr_cmd_prepare_copy(void) { return; }
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/**
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* Save site before DDR training command execute .
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* Keep empty when nothing to do.
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*/
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void ddr_cmd_site_save(void)
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{
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/* select ddrt bus path */
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reg->custom.ive_ddrt_mst_sel = ddr_read(DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4);
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ddr_write(reg->custom.ive_ddrt_mst_sel & 0xffffffdf, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4);
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/* turn on ddrt clock */
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reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT);
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/* enable ddrt0 clock */
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ddr_write(reg->custom.ddrt_clk_reg | (1U << 1), CRG_REG_BASE + PERI_CRG_DDRT);
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__asm__ __volatile__("nop");
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/* disable ddrt0 soft reset */
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ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(1U << 0)), CRG_REG_BASE + PERI_CRG_DDRT);
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/* disable rdqs anti-aging */
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reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL);
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ddr_write((reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL);
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#ifdef DDR_REG_BASE_PHY1
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reg->custom.phy1_age_compst_en = ddr_read(DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL);
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ddr_write((reg->custom.phy1_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL);
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#endif
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}
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/**
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* Restore site after DDR training command execute.
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* Keep empty when nothing to do.
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*/
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void ddr_cmd_site_restore(void)
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{
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/* restore ddrt bus path */
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ddr_write(reg->custom.ive_ddrt_mst_sel, DDR_REG_BASE_SYSCTRL + SYSCTRL_MISC_CTRL4);
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/* restore ddrt clock */
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ddr_write(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT);
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/* restore rdqs anti-aging */
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ddr_write(reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL);
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#ifdef DDR_REG_BASE_PHY1
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ddr_write(reg->custom.phy1_age_compst_en, DDR_REG_BASE_PHY1 + DDR_PHY_PHYRSCTRL);
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#endif
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}
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void ddr_training_save_reg_custom(void *reg, unsigned int mask) { return; }
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void ddr_training_restore_reg_custom(void *reg) { return; }
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/**
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* DDR clock select.
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* For ddr osc training.
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*/
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#ifdef DDR_PCODE_TRAINING_CONFIG
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int ddr_get_cksel(void)
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{
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int freq;
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unsigned int ddr_cksel;
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ddr_cksel = (ddr_read(CRG_REG_BASE + PERI_CRG_DDRCKSEL) >> 0x3) & 0x7;
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switch (ddr_cksel) {
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case 0x000:
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/* 24MHz */
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freq = 24;
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break;
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case 0x001:
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/* 450MHz */
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freq = 450;
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break;
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case 0x011:
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/* 300MHz */
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freq = 300;
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break;
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case 0x100:
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/* 297MHz */
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freq = 297;
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break;
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default:
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freq = 300;
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break;
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}
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return freq;
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}
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#endif
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