437 lines
12 KiB
C
Executable File
437 lines
12 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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#include <asm/arch-gk7202v300/platform.h>
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#include <common.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include "mmc_private.h"
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#ifdef CONFIG_GK_SDHCI
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#define MIN_FREQ 400000
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#define NOT_FOUND (-1)
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#define PHASE_SCALE 32
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#define EDGE_TUNING_PHASE_STEP 4
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#define SDIO_DRV_DLL_SRST_REQ (0x1 << 29)
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#define SDIO_CLK_EN (0x1 << 28)
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#define SDIO_SRST_REQ (0x1 << 27)
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#define SDIO_CLK_SEL (0x7 << 24)
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#define SDIO_CLK_SEL_400K (0x1 << 24)
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#define REG_EMMC_DRV_DLL_STATUS (CRG_REG_BASE + 0x210)
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#define REG_SDIO0_DRV_DLL_STATUS REG_EMMC_DRV_DLL_STATUS
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#define REG_SDIO1_DRV_DLL_STATUS (CRG_REG_BASE + 0x228)
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#define SDIO_DRV_DLL_LOCK BIT(15)
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#define SDIO_DRV_DLL_READY BIT(14)
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#define REG_EMMC_SAMPL_DLL_STATUS (CRG_REG_BASE + 0x208)
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#define REG_SDIO0_SAMPL_DLL_STATUS REG_EMMC_SAMPL_DLL_STATUS
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#define REG_SDIO1_SAMPL_DLL_STATUS (CRG_REG_BASE + 0x224)
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#define SDIO_SAMPL_DLL_SLAVE_READY BIT(0)
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#define REG_EMMC_SAMPL_DLL_CTRL (CRG_REG_BASE + 0x1f4)
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#define REG_SDIO0_SAMPL_DLL_CTRL REG_EMMC_SAMPL_DLL_CTRL
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#define REG_SDIO1_SAMPL_DLL_CTRL (CRG_REG_BASE + 0x22c)
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#define SDIO_SAMPL_DLL_SLAVE_EN BIT(16)
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#define REG_EMMC_SAMPLB_DLL_CTRL (CRG_REG_BASE + 0x1f8)
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#define REG_SDIO0_SAMPLB_DLL_CTRL REG_EMMC_SAMPLB_DLL_CTRL
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#define REG_SDIO1_SAMPLB_DLL_CTRL (CRG_REG_BASE + 0x21c)
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#define SDIO_SAMPLB_DLL_CLK_MASK (0x1f << 0)
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#define sdio_samplb_sel(phase) ((phase) << 0)
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#define REG_EMMC_DRV_DLL_CTRL (CRG_REG_BASE + 0x1fc)
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#define REG_SDIO0_DRV_DLL_CTRL REG_EMMC_DRV_DLL_CTRL
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#define REG_SDIO1_DRV_DLL_CTRL (CRG_REG_BASE + 0x220)
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#define SDIO_DRV_PHASE_SEL_MASK (0x1f << 24)
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#define sdio_drv_sel(phase) ((phase) << 24)
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#define REG_EMMC_DS_DLL_CTRL (CRG_REG_BASE + 0x200)
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#define EMMC_DS_DLL_MODE_SSEL BIT(13)
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#define EMMC_DS_DLL_SSEL_MASK 0x7f
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#define REG_EMMC_DS180_DLL_CTRL (CRG_REG_BASE + 0x204)
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#define EMMC_DS180_DLL_BYPASS BIT(15)
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#define REG_EMMC_DS180_DLL_STATUS (CRG_REG_BASE + 0x218)
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#define EMMC_DS180_DLL_READY BIT(0)
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#define IO_CFG_SR BIT(10)
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#define IO_CFG_PULL_DOWN BIT(9)
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#define IO_CFG_PULL_UP BIT(8)
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#define IO_CFG_DRV_STR_MASK (0xf << 4)
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#define io_cfg_drv_str_sel(str) ((str) << 4)
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#define REG_IO_CFG_BASE 0x100C0000
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/* EMMC_IOCFG */
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#define IO_CFG_EMMC_DATA_LINE_COUNT 4
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#define REG_CTRL_EMMC_CLK 0x0014
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#define REG_CTRL_EMMC_CMD 0x0018
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#define REG_CTRL_EMMC_DATA0 0x001c
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#define REG_CTRL_EMMC_DATA1 0x0028
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#define REG_CTRL_EMMC_DATA2 0x0024
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#define REG_CTRL_EMMC_DATA3 0x0020
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#define REG_CTRL_EMMC_DS 0x0058
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#define REG_CTRL_EMMC_RST 0x005c
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static unsigned int io_emmc_data_reg[IO_CFG_EMMC_DATA_LINE_COUNT] = {
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REG_CTRL_EMMC_DATA0, REG_CTRL_EMMC_DATA1,
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REG_CTRL_EMMC_DATA2, REG_CTRL_EMMC_DATA3
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};
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#define IO_CFG_SDIO0_DATA_LINE_COUNT 4
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#define REG_CTRL_SDIO0_CLK 0x0040
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#define REG_CTRL_SDIO0_CMD 0x0044
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#define REG_CTRL_SDIO0_DATA0 0x0048
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#define REG_CTRL_SDIO0_DATA1 0x004C
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#define REG_CTRL_SDIO0_DATA2 0x0050
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#define REG_CTRL_SDIO0_DATA3 0x0054
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static unsigned int io_sdio0_data_reg[IO_CFG_SDIO0_DATA_LINE_COUNT] = {
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REG_CTRL_SDIO0_DATA0, REG_CTRL_SDIO0_DATA1,
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REG_CTRL_SDIO0_DATA2, REG_CTRL_SDIO0_DATA3
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};
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#define CLK_100K 100000
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#define CLK_400K 400000
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#define CLK_25M 25000000
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#define CLK_50M 50000000
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#define CLK_90M 90000000
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#define CLK_112M 112000000
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#define CLK_150M 150000000
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#define CLK_198M 198000000
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static void bsp_enable_sample(struct sdhci_host *host);
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static void bsp_set_drv_phase(struct sdhci_host *host, unsigned int phase);
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static void bsp_set_sampl_phase(struct sdhci_host *host, unsigned int phase);
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static void bsp_wait_sampl_dll_slave_ready(struct sdhci_host *host);
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static void bsp_enable_card_clk(struct sdhci_host *host);
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static void bsp_disable_card_clk(struct sdhci_host *host);
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static void bsp_enable_internal_clk(struct sdhci_host *host);
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static void bsp_disable_internal_clk(struct sdhci_host *host);
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static int bsp_mmc_exec_tuning(struct sdhci_host *host, unsigned int opcode);
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static void bsp_dll_reset_assert(struct sdhci_host *host)
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{
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uintptr_t crg_addr;
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unsigned int reg;
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crg_addr = REG_EMMC_CRG;
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reg = readl(crg_addr);
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reg |= SDIO_DRV_DLL_SRST_REQ;
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writel(reg, crg_addr);
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}
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static void bsp_dll_reset_deassert(struct sdhci_host *host)
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{
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uintptr_t crg_addr;
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unsigned int reg;
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crg_addr = REG_EMMC_CRG;
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reg = readl(crg_addr);
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reg &= ~SDIO_DRV_DLL_SRST_REQ;
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writel(reg, crg_addr);
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}
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static void bsp_set_crg(struct sdhci_host *host, unsigned int clk)
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{
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uintptr_t crg_addr;
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unsigned int sel, reg;
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unsigned int clk_mux[] = {
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CLK_100K, CLK_400K, CLK_25M, CLK_50M,
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CLK_90M, CLK_112M, CLK_150M, CLK_198M
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};
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crg_addr = REG_EMMC_CRG;
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reg = readl(crg_addr);
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reg &= ~MMC_CLK_SEL_MASK;
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if (clk <= MIN_FREQ) {
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sel = 1;
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} else {
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for (sel = 0x6; sel > 0; sel--) {
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if (clk >= clk_mux[sel])
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break;
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}
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}
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reg |= mmc_clk_sel(sel);
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writel(reg, crg_addr);
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}
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static void bsp_wait_ds180_dll_ready(void)
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{
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unsigned int reg;
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unsigned int timeout = 20;
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do {
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reg = readl(REG_EMMC_DS180_DLL_STATUS);
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if (reg & EMMC_DS180_DLL_READY)
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return;
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udelay(1000); /* delay 1000us */
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timeout--;
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} while (timeout > 0);
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printf("DS180 DLL master not ready.\n");
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}
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static void bsp_mmc_priv_init(struct sdhci_host *host)
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{
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unsigned short ctrl;
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unsigned int reg;
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ctrl = sdhci_readw(host, SDHCI_MSHC_CTRL);
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ctrl &= ~SDHCI_CMD_CONFLIT_CHECK;
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sdhci_writew(host, ctrl, SDHCI_MSHC_CTRL);
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reg = sdhci_readl(host, SDHCI_AXI_MBIIU_CTRL);
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reg |= SDHCI_GM_WR_OSRC_LMT | SDHCI_GM_RD_OSRC_LMT;
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reg &= ~SDHCI_UNDEFL_INCR_EN;
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sdhci_writel(host, reg, SDHCI_AXI_MBIIU_CTRL);
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reg = sdhci_readl(host, SDHCI_MULTI_CYCLE);
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reg &= ~SDHCI_CMD_DLY_EN;
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reg |= SDHCI_EDGE_DETECT_EN | SDHCI_DATA_DLY_EN;
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sdhci_writel(host, reg, SDHCI_MULTI_CYCLE);
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}
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static void bsp_set_drv_str(unsigned int offset, unsigned int pull_up,
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unsigned int pull_down, unsigned int sr,
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unsigned int drv_str)
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{
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unsigned int reg;
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const uintptr_t crg_addr = REG_IO_CFG_BASE + offset;
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reg = readl(crg_addr);
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reg &= ~(IO_CFG_PULL_UP | IO_CFG_PULL_DOWN |
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IO_CFG_DRV_STR_MASK | IO_CFG_SR);
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reg |= (pull_up ? IO_CFG_PULL_UP : 0);
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reg |= (pull_down ? IO_CFG_PULL_DOWN : 0);
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reg |= (sr ? IO_CFG_SR : 0);
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reg |= io_cfg_drv_str_sel(drv_str);
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writel(reg, crg_addr);
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}
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static int sd_hardware_init(void)
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{
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unsigned int reg;
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/* clk enable */
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reg = readl(REG_EMMC_CRG);
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reg |= SDIO_CLK_EN;
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writel(reg, REG_EMMC_CRG);
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/* reset assert */
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reg = readl(REG_EMMC_CRG);
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reg |= SDIO_SRST_REQ | SDIO_DRV_DLL_SRST_REQ;
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writel(reg, REG_EMMC_CRG);
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udelay(25); /* delay 25us */
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/* reset deassert */
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reg &= ~SDIO_SRST_REQ;
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writel(reg, REG_EMMC_CRG);
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udelay(1); /* delay 1us */
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udelay(5000); /* delay 5000us */
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return 0;
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}
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static int emmc_hardware_init(void)
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{
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unsigned int reg;
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/* eMMC clk enable */
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reg = readl(REG_EMMC_CRG);
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reg |= SDIO_CLK_EN;
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writel(reg, REG_EMMC_CRG);
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/* eMMC reset assert */
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reg = readl(REG_EMMC_CRG);
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reg |= SDIO_SRST_REQ | SDIO_DRV_DLL_SRST_REQ;
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writel(reg, REG_EMMC_CRG);
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udelay(25); /* delay 25us */
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/* select 400K clk */
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reg = readl(REG_EMMC_CRG);
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reg &= ~SDIO_CLK_SEL;
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reg |= SDIO_CLK_SEL_400K;
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writel(reg, REG_EMMC_CRG);
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udelay(25); /* delay 25us */
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/* eMMC reset deassert */
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reg = readl(REG_EMMC_CRG);
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reg &= ~SDIO_SRST_REQ;
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writel(reg, REG_EMMC_CRG);
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udelay(1); /* delay 1us */
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return 0;
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}
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static void bsp_mmc_set_ioconfig(struct sdhci_host *host)
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{
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unsigned int reg;
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int i;
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if (host->type == MMC_TYPE_MMC) {
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reg = sdhci_readw(host, SDHCI_EMMC_CTRL);
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reg |= SDHCI_CARD_IS_EMMC;
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sdhci_writew(host, reg, SDHCI_EMMC_CTRL);
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switch (host->mmc->timing) {
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case MMC_TIMING_MMC_HS400:
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bsp_set_drv_str(REG_CTRL_EMMC_CLK, 0, 1, 0, 0x3); /* set drv level 3 */
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bsp_set_drv_str(REG_CTRL_EMMC_CMD, 1, 0, 0, 0x5); /* set drv level 5 */
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for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
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bsp_set_drv_str(
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io_emmc_data_reg[i], 1, 0, 0, 0x5); /* set drv level 5 */
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bsp_set_drv_str(REG_CTRL_EMMC_DS, 0, 1, 1, 0x3); /* set drv level 3 */
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bsp_set_drv_str(REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
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break;
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case MMC_TIMING_MMC_HS200:
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bsp_set_drv_str(REG_CTRL_EMMC_CLK, 0, 1, 0, 0x2); /* set drv level 2 */
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bsp_set_drv_str(REG_CTRL_EMMC_CMD, 1, 0, 1, 0x4); /* set drv level 4 */
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for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
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bsp_set_drv_str(
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io_emmc_data_reg[i], 1, 0, 1, 0x4); /* set drv level 4 */
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bsp_set_drv_str(REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
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break;
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case MMC_TIMING_MMC_HS:
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bsp_set_drv_str(REG_CTRL_EMMC_CLK, 0, 1, 1, 0x4); /* set drv level 4 */
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bsp_set_drv_str(REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6); /* set drv level 6 */
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for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
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bsp_set_drv_str(
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io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
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bsp_set_drv_str(REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
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break;
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case MMC_TIMING_LEGACY:
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case MMC_TIMING_MMC_DDR52:
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default:
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bsp_set_drv_str(REG_CTRL_EMMC_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
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bsp_set_drv_str(REG_CTRL_EMMC_CMD, 1, 0, 1, 0x6); /* set drv level 6 */
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for (i = 0; i < IO_CFG_EMMC_DATA_LINE_COUNT; i++)
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bsp_set_drv_str(
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io_emmc_data_reg[i], 1, 0, 1, 0x6); /* set drv level 6 */
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bsp_set_drv_str(REG_CTRL_EMMC_RST, 1, 0, 1, 0x3); /* set drv level 3 */
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break;
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}
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} else {
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switch (host->mmc->timing) {
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case MMC_TIMING_SD_HS:
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bsp_set_drv_str(REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
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bsp_set_drv_str(REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7); /* set drv level 7 */
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for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
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bsp_set_drv_str(
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io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
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break;
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case MMC_TIMING_LEGACY:
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default:
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bsp_set_drv_str(REG_CTRL_SDIO0_CLK, 0, 1, 1, 0x5); /* set drv level 5 */
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bsp_set_drv_str(REG_CTRL_SDIO0_CMD, 1, 0, 1, 0x7); /* set drv level 7 */
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for (i = 0; i < IO_CFG_SDIO0_DATA_LINE_COUNT; i++)
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bsp_set_drv_str(
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io_sdio0_data_reg[i], 1, 0, 1, 0x7); /* set drv level 7 */
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break;
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}
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}
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}
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static void bsp_set_phase(struct sdhci_host *host)
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{
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unsigned int drv_phase, sample_phase;
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if (host->mmc->timing == MMC_TIMING_MMC_HS400) {
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drv_phase = 9; /* 9 for 101.25 degree */
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sample_phase = host->tuning_phase;
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} else if (host->mmc->timing == MMC_TIMING_MMC_HS200) {
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drv_phase = 23; /* 23 for 258.75 degree */
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sample_phase = host->tuning_phase;
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} else if (host->mmc->timing == MMC_TIMING_MMC_HS) {
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drv_phase = 16; /* 16 for 180 degree */
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sample_phase = 4; /* 4 for 45 degree */
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} else if (host->mmc->timing == MMC_TIMING_SD_HS) {
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drv_phase = 20; /* 20 for 225 degree */
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sample_phase = 4; /* 4 for 45 degree */
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} else if (host->mmc->timing == MMC_TIMING_MMC_DDR52) {
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drv_phase = 8; /* 8 for 90 degree */
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sample_phase = host->tuning_phase;
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} else if (host->mmc->timing == MMC_TIMING_LEGACY) {
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drv_phase = 16; /* 16 for 180 degree */
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sample_phase = 0; /* 0 for degree */
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} else {
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drv_phase = 16; /* 16 for 180 degree */
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sample_phase = 0; /* 0 for degree */
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}
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bsp_set_drv_phase(host, drv_phase);
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bsp_enable_sample(host);
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bsp_set_sampl_phase(host, sample_phase);
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udelay(25); /* delay 25us */
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}
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static void bsp_wait_drv_dll_lock(struct sdhci_host *host)
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{
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unsigned int timeout = 20;
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unsigned int reg;
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uintptr_t reg_addr;
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reg_addr = host->type == MMC_TYPE_MMC ?
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REG_EMMC_DRV_DLL_STATUS : REG_SDIO0_DRV_DLL_STATUS;
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do {
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reg = readl(reg_addr);
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if (reg & SDIO_DRV_DLL_LOCK)
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return;
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udelay(1000); /* delay 1000us */
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timeout--;
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} while (timeout > 0);
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printf("sdhci: DRV DLL master not locked.\n");
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}
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static void bsp_enable_sampl_dll_slave(struct sdhci_host *host)
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{
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unsigned int reg;
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uintptr_t reg_addr;
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reg_addr = host->type == MMC_TYPE_MMC ?
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REG_EMMC_SAMPL_DLL_CTRL : REG_SDIO0_SAMPL_DLL_CTRL;
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reg = readl(reg_addr);
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reg |= SDIO_SAMPL_DLL_SLAVE_EN;
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writel(reg, reg_addr);
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}
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static int bsp_mmc_set_clk(struct sdhci_host *host, unsigned int clk)
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{
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bsp_dll_reset_assert(host);
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udelay(25); /* delay 25us */
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bsp_set_crg(host, clk);
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bsp_set_phase(host);
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udelay(25); /* delay 25us */
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if (clk > MMC_HIGH_52_MAX_DTR) {
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bsp_enable_sampl_dll_slave(host);
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bsp_dll_reset_deassert(host);
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}
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bsp_enable_internal_clk(host);
|
|
|
|
if (clk > MMC_HIGH_52_MAX_DTR) {
|
|
bsp_wait_drv_dll_lock(host);
|
|
bsp_wait_sampl_dll_slave_ready(host);
|
|
bsp_wait_ds180_dll_ready();
|
|
}
|
|
|
|
bsp_enable_card_clk(host);
|
|
udelay(100); /* delay 100us */
|
|
|
|
return 0;
|
|
}
|
|
|
|
#include "bsp_sdhci.c"
|
|
#endif |