509 lines
12 KiB
C
Executable File
509 lines
12 KiB
C
Executable File
/*
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* Copyright (c) Hunan Goke,Chengdu Goke,Shandong Goke. 2021. All rights reserved.
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*/
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#ifndef __VOU_DEF_H__
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#define __VOU_DEF_H__
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#ifdef __cplusplus
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extern "C" {
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#endif /* end of #ifdef __cplusplus */
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#define VO_BASE_ADDR 0x11280000
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#define VO_VHD_BASE_ADDR 0x800
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#define VO_GFX_BASE_ADDR 0x6000
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#define VO_HC_BASE_ADDR 0x9800
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#define VO_WBC0_BASE_ADDR 0xac00
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#define VO_WBC1_BASE_ADDR 0xa400
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#define VO_DHD_BASE_ADDR 0xc000
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#define VO_DSD_BASE_ADDR 0xc800
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#define VHD_REG_LEN 0x1000
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#define VSD_REG_LEN 0x1000
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#define GFX_REG_LEN 0x800
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#define HC_REG_LEN 0x800
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#define WBC_REG_LEN 0x400
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#define DHD_REG_LEN 0x400
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#define DSD_REG_LEN 0x400
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#define INTF_REG_LEN 0x100
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#define INTF_REGS_LEN 0x100
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#define VHD_REGS_LEN 0x1000 /* len of V0's regs */
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#define VSD_REGS_LEN 0x1000
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#define GFX_REGS_LEN 0x800
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#define WBC_REGS_LEN 0x400
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#define DHD_REGS_LEN 0x1000
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#define DSD_REGS_LEN 0x400
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#define INTF_REGS_LEN 0x100
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#define VID_REGS_LEN 0x200 /* len of VID regs */
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#define GRF_REGS_LEN 0x200 /* len of GFX regs */
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#define rgb_r(c) (((c) & 0xff0000) >> 16)
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#define rgb_g(c) (((c) & 0xff00) >> 8)
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#define rgb_b(c) ((c) & 0xff)
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#define ZME_HPREC (1 << 20)
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#define ZME_VPREC (1 << 12)
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#define MAX_OFFSET 3
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#define MIN_OFFSET (-1)
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#define CHANNEL_DHD_START 0
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#define CHANNEL_DHD_END 1
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#define CHANNEL_DSD_START 2
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#define CHANNEL_DSD_END 2
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#define MULTI_AREA_CFG_LEN (4 * 8)
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#define MULTI_AREA_1RGN 1
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#define MULTI_AREA_4RGN 4
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#define MULTI_AREA_32RGN 32
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#define MULTI_AREA_64RGN 64
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typedef enum {
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HAL_DISP_CHANNEL_DHD0 = 0,
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HAL_DISP_CHANNEL_DHD1 = 1,
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HAL_DISP_CHANNEL_WBC = 2,
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HAL_DISP_CHANNEL_DSD0 = 3,
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HAL_DISP_CHANNEL_BUTT
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} hal_disp_outputchannel;
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typedef enum {
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HAL_DISP_LAYER_VHD0 = 0,
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HAL_DISP_LAYER_VHD1 = 1,
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HAL_DISP_LAYER_VHD2 = 2,
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HAL_DISP_LAYER_VSD0 = 3,
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HAL_DISP_LAYER_GFX0 = 4, /* fb0 */
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HAL_DISP_LAYER_GFX1 = 5, /* fb2 */
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HAL_DISP_LAYER_HC0 = 6, /* G2 is HC0 fb3 */
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HAL_DISP_LAYER_HC1 = 7, /* G3 is HC1 fb4 */
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HAL_DISP_LAYER_GFX4 = 8, /* fb1 */
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HAL_DISP_LAYER_WBC_G0 = 9,
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HAL_DISP_LAYER_WBC_G4 = 10,
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HAL_DISP_LAYER_WBC_D = 11,
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HAL_DISP_LAYER_TT = 12,
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HAL_DISP_LAYER_WBC = 13,
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HAL_DISP_LAYER_BUTT,
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HAL_DISP_INVALID_LAYER = -1
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} hal_disp_layer;
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#define HAL_DISP_LAYER_GFX2 HAL_DISP_LAYER_HC0
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#define HAL_DISP_LAYER_GFX3 HAL_DISP_LAYER_HC1
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#define LAYER_VHD_START HAL_DISP_LAYER_VHD0
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#define LAYER_VHD_END HAL_DISP_LAYER_VHD0
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#define LAYER_VSD_START HAL_DISP_LAYER_VSD0
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#define LAYER_VSD_END HAL_DISP_LAYER_VSD0
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#define LAYER_GFX_START HAL_DISP_LAYER_GFX0
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#define LAYER_GFX_END HAL_DISP_LAYER_GFX0
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#define LAYER_WBC_START HAL_DISP_LAYER_WBC_D
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#define LAYER_WBC_END HAL_DISP_LAYER_WBC_D
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typedef enum {
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HAL_DISP_INTERLACE = 0,
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HAL_DISP_PROGRESSIVE = 1,
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HAL_DISP_TOP,
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HAL_DISP_BOTTOM,
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HAL_DISP_DATARMODE_BUTT
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} hal_disp_datarmode;
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typedef enum {
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HAL_INPUTFMT_Y_CB_CR_SEMIPLANAR_400 = 0x1,
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HAL_INPUTFMT_Y_CB_CR_SEMIPLANAR_411_1X4 = 0x2,
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HAL_INPUTFMT_Y_CB_CR_SEMIPLANAR_420 = 0x3,
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HAL_INPUTFMT_Y_CB_CR_SEMIPLANAR_422 = 0x4,
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HAL_INPUTFMT_Y_CB_CR_SEMIPLANAR_422_1X2 = 0x4,
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HAL_INPUTFMT_Y_CB_CR_SEMIPLANAR_444 = 0x5,
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HAL_INPUTFMT_Y_CB_CR_SEMIPLANAR_411_4X1 = 0x6,
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HAL_INPUTFMT_Y_CB_CR_SEMIPLANAR_422_2X1 = 0x7,
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HAL_INPUTFMT_CB_Y_CR_Y_PACKAGE_422 = 0x9,
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HAL_INPUTFMT_Y_CB_Y_CR_PACKAGE_422 = 0xa,
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HAL_INPUTFMT_Y_CR_Y_CB_PACKAGE_422 = 0xb,
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HAL_INPUTFMT_Y_CB_CR_PACKAGE_444 = 0x1000,
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HAL_INPUTFMT_CLUT_1BPP = 0x00,
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HAL_INPUTFMT_CLUT_2BPP = 0x10,
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HAL_INPUTFMT_CLUT_4BPP = 0x20,
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HAL_INPUTFMT_CLUT_8BPP = 0x30,
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HAL_INPUTFMT_ACLUT_44 = 0x38,
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HAL_INPUTFMT_RGB_444 = 0x40,
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HAL_INPUTFMT_RGB_555 = 0x41,
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HAL_INPUTFMT_RGB_565 = 0x42,
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HAL_INPUTFMT_CB_Y_CR_Y_PACKAGE_422_GRC = 0x43,
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HAL_INPUTFMT_Y_CB_Y_CR_PACKAGE_422_GRC = 0x44,
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HAL_INPUTFMT_Y_CR_Y_CB_PACKAGE_422_GRC = 0x45,
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HAL_INPUTFMT_ACLUT_88 = 0x46,
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HAL_INPUTFMT_ARGB_4444 = 0x48,
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HAL_INPUTFMT_ARGB_1555 = 0x49,
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HAL_INPUTFMT_RGB_888 = 0x50,
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HAL_INPUTFMT_Y_CB_CR_888 = 0x51,
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HAL_INPUTFMT_ARGB_8565 = 0x5a,
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HAL_INPUTFMT_ARGB_6666 = 0x5b,
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HAL_INPUTFMT_KRGB_888 = 0x60,
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HAL_INPUTFMT_ARGB_8888 = 0x68,
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HAL_INPUTFMT_A_Y_Cb_CR_8888 = 0x69,
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HAL_INPUTFMT_RGBA_4444 = 0xc8,
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HAL_INPUTFMT_RGBA_5551 = 0xc9,
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HAL_INPUTFMT_RGBA_6666 = 0xd8,
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HAL_INPUTFMT_RGBA_5658 = 0xda,
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HAL_INPUTFMT_RGBA_8888 = 0xe8,
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HAL_INPUTFMT_Y_CB_CR_A_8888 = 0xe9,
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HAL_DISP_PIXELFORMAT_BUTT
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} hal_disp_pixel_format;
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typedef enum {
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HAL_DISP_INTFDATAFMT_SPCBYCRY_422 = 0x0,
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HAL_DISP_INTFDATAFMT_SPYCBYCR_422 = 0x1,
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HAL_DISP_INTFDATAFMT_SPYCRYCB_422 = 0x2,
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HAL_DISP_INTFDATAFMT_ARGB8888 = 0x3,
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HAL_DISP_INTFDATAFMT_YCBCR420 = 0x4,
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HAL_DISP_INTFDATAFMT_YCBCR422 = 0x5,
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HAL_DISP_INTFDATAFMT_BUTT
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} hal_disp_intfdatafmt;
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typedef enum {
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VDP_PROC_FMT_SP_420 = 0x0,
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VDP_PROC_FMT_SP_422 = 0x1,
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VDP_PROC_FMT_SP_444 = 0x2,
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VDP_PROC_FMT_RGB_888 = 0x3,
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VDP_PROC_FMT_RGB_444 = 0x4,
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VDP_PROC_FMT_BUTT
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} vdp_proc_fmt;
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typedef enum {
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HAL_CS_UNKNOWN = 0,
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HAL_CS_BT601,
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HAL_CS_BT709,
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HAL_CS_RGB,
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HAL_CS_BUTT
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} hal_cs;
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typedef enum {
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HAL_CSC_MODE_NONE = 0,
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HAL_CSC_MODE_BT601_TO_BT601,
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HAL_CSC_MODE_BT709_TO_BT709,
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HAL_CSC_MODE_RGB_TO_RGB,
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HAL_CSC_MODE_BT601_TO_BT709,
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HAL_CSC_MODE_BT709_TO_BT601,
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HAL_CSC_MODE_BT601_TO_RGB_PC,
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HAL_CSC_MODE_BT709_TO_RGB_PC,
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HAL_CSC_MODE_BT2020_TO_RGB_PC,
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HAL_CSC_MODE_RGB_TO_BT601_PC,
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HAL_CSC_MODE_RGB_TO_BT709_PC,
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HAL_CSC_MODE_RGB_TO_BT2020_PC,
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HAL_CSC_MODE_BT601_TO_RGB_TV,
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HAL_CSC_MODE_BT709_TO_RGB_TV,
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HAL_CSC_MODE_RGB_TO_BT601_TV,
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HAL_CSC_MODE_RGB_TO_BT709_TV,
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HAL_CSC_MODE_BUTT
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} hal_csc_mode;
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typedef enum {
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HAL_DISP_BIT_WIDTH_1 = 0x0,
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HAL_DISP_BIT_WIDTH_2 = 0x1,
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HAL_DISP_BIT_WIDTH_3 = 0x2,
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HAL_DISP_BIT_WIDTH_BUTT
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} hal_disp_bit_width;
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typedef enum {
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HAL_CCD_IMGID_INVALID,
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HAL_CCD_IMGID_1080P60,
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HAL_CCD_IMGID_1080P30_ODD,
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HAL_CCD_IMGID_1080P30_EVEN,
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} hal_ccd_imgid;
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typedef enum {
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HAL_T_FIRST = 0,
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HAL_B_FIRST = 1,
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HAL_VHD_FOD_BUTT
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} hal_vhd_fod;
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/* vou coef load mode */
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typedef enum {
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HAL_DISP_COEFMODE_HORL = 0,
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HAL_DISP_COEFMODE_HORC,
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HAL_DISP_COEFMODE_VERL,
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HAL_DISP_COEFMODE_VERC,
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HAL_DISP_COEFMODE_LUT,
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HAL_DISP_COEFMODE_GAM,
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HAL_DISP_COEFMODE_ACC,
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HAL_DISP_COEFMODE_ALL
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} hal_disp_coefmode;
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/* vou zoom mode */
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typedef enum {
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HAL_DISP_ZMEMODE_HORL = 0,
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HAL_DISP_ZMEMODE_HORC,
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HAL_DISP_ZMEMODE_VERL,
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HAL_DISP_ZMEMODE_VERC,
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HAL_DISP_ZMEMODE_HOR,
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HAL_DISP_ZMEMODE_VER,
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HAL_DISP_ZMEMODE_ALPHA,
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HAL_DISP_ZMEMODE_ALPHAV,
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HAL_DISP_ZMEMODE_VERT,
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HAL_DISP_ZMEMODE_VERB,
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HAL_DISP_ZMEMODE_ALL,
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HAL_DISP_ZMEMODE_NONL,
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HAL_DISP_ZMEMODE_BUTT
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} hal_disp_zmemode;
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typedef enum {
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HAL_DISP_ZME_OUTFMT420 = 0,
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HAL_DISP_ZME_OUTFMT422,
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HAL_DISP_ZME_OUTFMT444,
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HAL_DISP_ZME_OUTFMT_BUTT
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} hal_disp_zme_outfmt;
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/* vou CBM MIXER */
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typedef enum {
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HAL_CBMMIX1 = 0,
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HAL_CBMMIX2,
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HAL_CBMMIX3,
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HAL_CBMMIX1_BUTT
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} hal_cbmmix;
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/* vou graphic layer data extend mode */
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typedef enum {
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HAL_GFX_BITEXTEND_1ST = 0,
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HAL_GFX_BITEXTEND_2ND = 0x2,
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HAL_GFX_BITEXTEND_3RD = 0x3,
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HAL_GFX_BITEXTEND_BUTT
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} hal_gfx_bitextend;
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/* vou acm block id information */
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typedef enum {
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HAL_ACMBLK_ID0,
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HAL_ACMBLK_ID1,
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HAL_ACMBLK_ID2,
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HAL_ACMBLK_ID3,
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HAL_ACMBLK_ALL,
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HAL_ACMBLK_BUTT
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} hal_acmblk_id;
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typedef enum {
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HAL_DAC_SEL_HDDATE = 0x0,
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HAL_DAC_SEL_VGA = 0x01,
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} hal_dac_sel;
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typedef enum {
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HAL_DISP_SYNC_MODE_TIMING = 0x0,
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HAL_DISP_SYNC_MODE_SIGNAL = 0x1,
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HAL_DISP_SYNC_MODE_BUTT
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} hal_disp_sync_mode;
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typedef enum {
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HAL_GFX_LINE_TYPE_HYBRID,
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HAL_GFX_LINE_TYPE_VLC,
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HAL_GFX_LINE_TYPE_FLC,
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HAL_GFX_LINE_TYPE_BUTT,
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} hal_gfx_linetype;
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typedef enum {
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HAL_GFX_LINE_LEN_128,
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HAL_GFX_LINE_LEN_256,
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HAL_GFX_LINE_LEN_512,
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HAL_GFX_LINE_LEN_ALLLINE,
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HAL_GFX_LINE_LEN_BUTT,
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} hal_gfx_linelen;
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/* RM frame or filed infomation */
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typedef enum {
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HAL_IFIRMODE_DISEN = 0,
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HAL_IFIRMODE_COPY,
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HAL_IFIRMODE_DOUBLE,
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HAL_IFIRMODE_6TAPFIR,
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HAL_IFIRMODE_BUTT
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} hal_ifirmode;
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typedef enum {
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HAL_HFIRMODE_MEDEN = 0,
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HAL_HFIRMODE_COPY,
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HAL_HFIRMODE_DOUBLE,
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HAL_HFIRMODE_6TAPFIR,
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HAL_HFIRMODE_BUTT
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} hal_hfirmode;
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/* vou mixer prio id */
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typedef enum {
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HAL_DISP_MIX_PRIO0 = 0,
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HAL_DISP_MIX_PRIO1,
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HAL_DISP_MIX_PRIO2,
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HAL_DISP_MIX_PRIO3,
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HAL_DISP_MIX_BUTT
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} hal_disp_mix_prio;
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/* LTI/CTI mode */
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typedef enum {
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HAL_DISP_TIMODE_LUM = 0,
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HAL_DISP_TIMODE_CHM,
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HAL_DISP_TIMODE_ALL,
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HAL_DISP_TIMODE_NON,
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HAL_DISP_TIMODE_BUTT,
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} hal_disp_timode;
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typedef struct {
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gk_u32 synm;
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gk_u32 iop;
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gk_u8 intfb;
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gk_u16 vact;
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gk_u16 vbb;
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gk_u16 vfb;
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gk_u16 hact;
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gk_u16 hbb;
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gk_u16 hfb;
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gk_u16 hmid;
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gk_u16 bvact;
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gk_u16 bvbb;
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gk_u16 bvfb;
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gk_u16 hpw;
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gk_u16 vpw;
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gk_u32 idv;
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gk_u32 ihs;
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gk_u32 ivs;
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} hal_disp_syncinfo;
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typedef struct {
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gk_u32 dither_sed_y0;
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gk_u32 dither_sed_u0;
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gk_u32 dither_sed_v0;
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gk_u32 dither_sed_w0;
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gk_u32 dither_sed_y1;
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gk_u32 dither_sed_u1;
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gk_u32 dither_sed_v1;
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gk_u32 dither_sed_w1;
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gk_u32 dither_sed_y2;
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gk_u32 dither_sed_u2;
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gk_u32 dither_sed_v2;
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gk_u32 dither_sed_w2;
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gk_u32 dither_sed_y3;
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gk_u32 dither_sed_u3;
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gk_u32 dither_sed_v3;
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gk_u32 dither_sed_w3;
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} hal_disp_dihter_sed;
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typedef enum {
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/* the numbers are to define the enum, not magic numbers */
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HAL_DISP_INTF_CVBS = (0x01L << 0),
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HAL_DISP_INTF_HDDATE = (0x01L << 1),
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HAL_DISP_INTF_VGA = (0x01L << 2),
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HAL_DISP_INTF_BT656 = (0x01L << 3),
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HAL_DISP_INTF_BT1120 = (0x01L << 4),
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HAL_DISP_INTF_HDMI = (0x01L << 5),
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HAL_DISP_INTF_LCD = (0x01L << 6),
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HAL_DISP_INTF_DATE = (0x01L << 7),
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HAL_DISP_INTF_LCD_6BIT = (0x01L << 9),
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HAL_DISP_INTF_LCD_8BIT = (0x01L << 10),
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HAL_DISP_INTF_LCD_16BIT = (0x01L << 11),
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HAL_DISP_INTF_LCD_18BIT = (0x01L << 12),
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HAL_DISP_INTF_LCD_24BIT = (0x01L << 13),
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HAL_DISP_INTF_MIPI = (0x01L << 14),
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HAL_DISP_INTF_BUTT = (0x01L << 15),
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} hal_disp_intf;
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typedef struct {
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gk_u32 f_inv;
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gk_u32 vs_inv;
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gk_u32 hs_inv;
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gk_u32 dv_inv;
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} hal_disp_syncinv;
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typedef enum {
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HAL_MULTICHN_EN_1P1C = 0x1,
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HAL_MULTICHN_EN_2P1C = 0x2,
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} hal_multi_chn;
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/* vou background color */
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typedef struct {
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gk_u16 bkg_a;
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gk_u16 bkg_y;
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gk_u16 bkg_cb;
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gk_u16 bkg_cr;
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} hal_disp_bkcolor;
|
|
|
|
typedef struct {
|
|
gk_u16 clip_low_y;
|
|
gk_u16 clip_low_cb;
|
|
gk_u16 clip_low_cr;
|
|
|
|
gk_u16 clip_high_y;
|
|
gk_u16 clip_high_cb;
|
|
gk_u16 clip_high_cr;
|
|
} hal_disp_clip;
|
|
|
|
typedef struct {
|
|
gk_s32 x;
|
|
gk_s32 y;
|
|
gk_u32 width;
|
|
gk_u32 height;
|
|
} gk_rect;
|
|
|
|
typedef struct {
|
|
gk_u32 fbdiv;
|
|
gk_u32 frac;
|
|
gk_u32 refdiv;
|
|
gk_u32 postdiv1;
|
|
gk_u32 postdiv2;
|
|
} vo_user_intfsync_pll;
|
|
|
|
typedef enum {
|
|
VO_CLK_SOURCE_PLL = 0,
|
|
VO_CLK_SOURCE_LCDMCLK,
|
|
VO_CLK_SOURCE_BUTT
|
|
} vo_clk_source;
|
|
|
|
typedef struct {
|
|
vo_clk_source clk_source;
|
|
union {
|
|
vo_user_intfsync_pll user_sync_pll;
|
|
gk_u32 lcd_m_clk_div;
|
|
};
|
|
} vo_user_intfsync_attr;
|
|
|
|
typedef struct {
|
|
vo_user_intfsync_attr user_intf_sync_attr;
|
|
gk_u32 pre_div;
|
|
gk_u32 dev_div;
|
|
gk_bool clk_reverse;
|
|
} vo_user_intfsync_info;
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif /* end of #ifdef __cplusplus */
|
|
#endif /* end of __VOU_DEF_H__ */
|
|
|